Abstract: A read-only-memory for use in an electronic calculator or the like, implemented in a large-scale-integrated MOS semiconductor chip. The ROM is designed to save area on the chip by employing a virtual ground feature and conserve power by a precharge system. The memory cells are in an array defining X and Y lines, with the presence or absence of a bit being determined by thin oxide under an X line between adjacent Y lines. Ground lines are provided for groups of Y lines, and the Y-decode matrix includes an arrangement for connecting a selected Y-line to a non-adjacent ground line. Only the X decode section is precharged rather than all the X lines. The entire decode and read out is accomplished in a small part of the instruction cycle of the calculator.

Abstract: An arrangement is shown for controlling transmission of blocks of information to and from a plurality of major components of a digital computer system interconnected by common buses. The disclosed arrangement operates so that any component of the system may normally seize, on a nonpriority basis, one of the buses at the beginning of any time slot defined by two successive clock pulses generated by a single source and applied to all components simultaneously; however, if a special instruction is encountered during execution of a program, any component may retain a bus for more than one time slot. The disclosed arrangement also permits error checking of transmitted information from a given major component without interfering with transmission from any other major component and automatically causes retransmission of any block of information found to be improperly transmitted originally.

Abstract: Circuits and method for synchronizing and checking a plurality of time-of-day (TOD) clocks in a multiprocessing system. Unique hardware synchronizes the low order part of the TOD clocks and a unique method synchronizes the high order part in the same clocks by using carry pulses derived from an intermediate bit position in each TOD clock. The carry pulses from all TOD clocks are combined in an OR circuit with each clock to provide common carry pulses for synchronizing each TOD clock in the system.

Abstract: Disclosed is a system for sorting information such as used, for example, in inventory control. New items to be sorted are fetched from a memory unit and are stored as buffered items in buffer stores. Comparators compare each new item from the memory unit with each of the buffered items in the buffer stores and with a lower limit and an upper limit. Item sort address registers store addresses which define the sorted order of the items in the buffer stores. After comparison of each new item, the item sort address registers are updated by the results of the comparison to establish a new sorted order and to cause rejected buffered items to be deleted from the buffer stores to make room for accepted new items. Reformatting apparatus is provided for reformatting items from the memory unit which have variable length and different weight fields such as prefix, body and suffix fields. Apparatus is provided for recognizing control fields which cause items to be ignored or included within the sorting process.