Abstract: A non-linear amplifier circuit comprises a low band eliminating filter for receiving an input signal from an input terminal, a logarithmic amplifier and an adder for adding the output signal of this logarithmic amplifier and the input signal with a predetermined polarity relationship to produce an output signal and sending this output signal to an output terminal. The logarithmic amplifier comprises an amplifier for receiving the output signal of the low band eliminating filter, a bidirectional logarithmic element and a resistor coupled in parallel thereto between the input and output terminals of the amplifier.

Abstract: A video-rate coordinate remapper includes a memory for storing a plurality of transformations on look-up tables for remapping input images from one coordinate system to another. Such transformations are operator selectable. The remapper includes a collective processor by which certain input pixels of an input image are transformed to a portion of the output image in a many-to-one relationship. The remapper includes an interpolative processor by which the remaining input pixels of the input image are transformed to another portion of the output image in a one-to-many relationship. The invention includes certain specific transforms for creating output images useful for certain defects of visually impaired people. The invention also includes circuitry for shifting input pixels and circuitry for scrolling the output matrix.

Abstract: Apparatus for converting a signal having a substantially continuous frequency spectrum to a signal having its energy concentrated at multiples of the line frequency of a video signal, includes circuitry for apportioning the signal into two intermediate signals including, in part, mutually exclusive portions of the original signal and inverting the polarity of portions of the signal. The two intermediate signals are thereafter used to quadrature phase modulate a carrier of multiple line frequency to generate a signal for combining with a video signal for transmission.

Abstract: A P/S converter converts parallel digital video signals such as a luminance signal Y and color difference signals R-Y and B-Y to serial digital video signals which are written into a semiconductor memory. The serial digital video signals read from the semiconductor memory are converted in a S/P converter to parallel digital video signals. A clock generator supplies clock signals to the P/S and S/P converters, such that a phase of the clock signals for the S/P converter has a predetermined relation to a phase of the clock signals for the P/S converter. As a result, the number of input and output pins is decreased in the semiconductor memory to result in the decreased of the fabricating cost thereof.

Abstract: A high definition television system includes an encoder for encoding a video source signal having a horizontal bandwidth of about 28-30 MHz for transmission through a 6 MHz RF channel. The video source signal is provided in the form of a plurality of horizontal video lines occurring at a vertical rate equal to the NTSC field repetition rate and at a predetermined horizontal rate greater than the NTSC horizontal scanning rate. The video lines of the source signal are encoded for transmission at NTSC vertical and horizontal rates, with the lines representing the lower frequencies of the video source signal being transmitted at a higher temporal rate than the lines representing the higher frequencies. The transmitted lines are converted to a plurality of display lines by a receiver for display at a vertical rate equal to the NTSC field repetition rate and at a horizontal rate equal to the predetermined horizontal rate.

Abstract: There is provided an image processing apparatus comprising an image signal generator having a first processing unit for processing the image signal in a first mode and generating a first processed signal, a discriminator for discriminating characteristics of the image signal, the discriminator having a selector for selecting the first processed signal according to a discrimination result; and a pulse width modulated signal generator for processing the first processed signal from the selector by using a pattern signal and for generating a pulse width modulated signal.

Abstract: An interpolation circuit, in which a digital signal produced by sampling and quantizing an analog information sequentially is encoded so that, in case a certain one of the encoded sample data is erroneous, a correct data in place of the erroneous sample data is prepared as an interpolation data by interpolating other correct sample data. The interpolation circuit includes: a first extrapolation circuit for generating a first extrapolation data by extrapolating two sample data preceding the erroneous sample data to the position of said erroneous sample data, a second extrapolation circuit for generating a second extrapolation data by extrapolating the two sample data succeeding the erroneous sample data to the position of the erroneous sample data, and an averaging circuit for generating the interpolation data by arithmetically averaging the first and second extrapolation data.

Abstract: A televison signal transmission system comprising transmitting stations and receiving stations. Each transmitting station has a signal-transmitting circuit and a signal-superposing circuit. The signal-superposing circuit superposes a discriminant signal on a television signal during a vertical-blanking interval of the television signal. The discriminant signal is required for selecting the television signal. The signal-transmitting circuit inserts the television signals, containing the discriminant signal, into the communication channel assigned to the transmitting station, and then transmits the television signal to the receiving stations. Each receiving station has a signal-receiving circuit, a signal-detecting circuit, and a signal-selecting circuit. The signal-receiving circuit receives the television signals transmitted from the transmitting stations.

Abstract: The invention provides a TV of internal PiP type for receiving the character multibroadcasting which installs the character multiblock having PiP block which is constructed so that a complex signal or a composite image signal of the IF circuit are selected at a switching board and is applied to a Y/C processor and a PiP processor, the device comprising, a teletext-processing circuit for providing a composite synchronization signal and RGB signal after extraction and decoding of the character multiinformation included in the composite image signal which is provided from the intermediate frequency(IF) circuit an encoder for providing a first composite image signal by encoding said composite synchronization signal and RGB signal, and a switch for providing the composite image signals provided from said IF circuit and the encoder, respectively, to the switching board by switching of a control signal provided from the teletext-processing circuit.

Abstract: A receiver-compatible EDTV system wherein enhancement information is adaptively modulated to suppress channel noise and is transmitted outside the usable picture area of a receiver compatible signal of the receiver compatible EDTV system.

Abstract: An address control circuit for a video memory of a multi-image display system. The circuit includes a video signal source, a video memory for storing the video signal, an address holding circuit for controlling write addresses of the video memory which outputs address values during a video image period and holds address value corresponding to a start instance of a blanking period during the blanking period and a bias generating circuit for positioning address areas of the video memory in which the video signal is stored.

Abstract: Horizontal synchronizing signals included in a video signal are inputted to a PLL circuit. A counter as a divider in the PLL circuit outputs signals which are synchronized with the horizontal synchronizing signals. A gate pulse generator counts the output pulses of counter and produces a control signal for controlling a phase comparator as one of elements of the PLL circuit. The operation of phase comparator is stopped in vertical intervals in accordance with the control signal so that the phase comparator is not affected by signals which are included in the video signal and are not synchronized with the horizontal synchronizing signals. Thus, the PLL circuit produces pulses which are synchronized with the horizontal synchronizing signals in a wide frequency range.

Abstract: A video camera for photographing papers which is used in a video apparatus for office automation such as an electronic image input apparatus. The video camera includes an image pickup part for picking up the images of papers and a signal processing part for converting a video signal obtained from the image pickup part into a given format. The signal processing part includes a .gamma. correction circuit for correcting the .gamma. value of the video signal obtained from the image pickup part. The .gamma. correction circuit has at least two discrete .gamma. correction values so that a proper .gamma. correction value can be selected according to the objects to be photographted. For example, when the objects to be photographted are black and white papers, a value of 0.45 or greater is selected for the .gamma. correction value. By selecting the .gamma.

Abstract: A monostable, that is triggered by either positive or negative polarity horizontal sync pulses, supplies the horizontal deflection system of a monitor. A first transistor of the monostable has its emitter and its base connected through oppositely poled diodes to the horizontal sync input terminal of the monitor. Incoming horizontal sync pulses of either polarity trigger a respective one of the diodes to drive the first transistor into conduction. The time constant of the first transistor is selected to be slightly greater than the duration of the input sync pulses to preclude the monostable triggering on the trailing edge of a sync pulse.

Abstract: A keyed type synchronization wave detecting circuit comprises a phase wave detector for synchronizing and wave detecting a composite video signal responsive to a signal for wave detection. A synchronizing signal generator provides a horizontal synchronizing signal controlled by the frequency of a horizontal synchronizing signal of the composite video signal. A keying pulse generator provides a keying pulse signal from the synchronizing signal of the synchronizing signal generator. A phase controller outputs a phase difference signal in accordance with the difference in phase between the signal for wave detection and a carrier of the composite video signal such that the phase difference approaches a predetermined level, the phase controller having a comparator for performing a keying outputting operation of the phase difference signal by the input of the keying pulse signal, and a filter for removing the high frequency component of the phase difference signal and forming a control signal.

Abstract: A video interface circuit for displaying the output of a video camera on a video monitor of the type used for displaying computer output data. In a first mode of operation, data from a video camera is stored in a first video memory while data previously stored in a second video memory is displayed on a video monitor. In a second mode of operation, there is provided the further steps of displaying information previously stored in the first and second video memories alternately on the video monitor. In a third mode of operation, data previously stored in the first and second video memories is read out one word at a time. If a predetermined bit in the word read from the second video memory has a first predetermined logical level, the word read from the first video memory is displayed on the video monitor. Alternately, if the predetermined bit in the word read from the second video memory has a second predetermined level, the word read from the second video memory is displayed on the video monitor.

Abstract: A teletext decoder comprises a main memory (M2) which includes a raw data buffer (RDB) in rows RD0 to RDn of which teletext data packets and non-teletext "junk" data packets are stored in the order in which they are received, and a reformatting buffer (RB) to rows R0 to R31 of which the data packets stored in the RDB memory are transferred, the data packets in the RB memory being stored in a given numeral sequence. Each of the rows R0 to R31 of the buffer (RB) has a status buffer (SB) byte B0 to B31 respectively, associated with it for indicating whether the corresponding data packet has been received out of its correct given numerical sequence, and thereby being a possible non-teletext "junk" data packet which may be subsequently overwritten by a valid data packet.

Abstract: A video display device comprising a display panel which has a large number of luminescent display cells arranged in an X-Y matrix and with a common drive circuit for applying an input video signal which substantially reduces the number of drive circuits by at least a factor of two and wherein a switching circuit switches the input video signal from a first plurality of luminescent display cells to adjacent luminescent display cells at every field period of the input video signal so as to reduce at least by one half the number of drive units required in the display device.

Abstract: A character multiplex broadcasting receiving apparatus is provided for reducing and displaying a plurality of character figure images including header information and text information. In the invention, to simultaneously display a plurality of character figure images, division signals are formed from a horizontal pulse, a vertical pulse, and a clock pulse (chrominance subcarrier frequency f.sub.sc .times.4) to designate areas on the CRT. Either and animation image (television image) or a character image to display character figure information is designated for each divided picture plane and a plurality of character figure images are simultaneously displayed.

Abstract: A television encoder for generating a receiver-compatible signal from a production video signal containing enhancement information which cannot be displayed on a standard receiver, the receiver-compatible signal being compatible with the standard receiver, the encoder including a filter bank for dividing the video signal into at least two groups of spatial frequency components including a first group and a second group, the first group containing members which when combined together form a standard video signal which is displayed by the standard receiver and the second group containing the enhancement information; a quantizer for quantizing at least one member of the first group; a combiner for adding at least one member of the second group to a quantized member of the first group to produce a modified first group; and a synthesizer for combining the members of the modified first group to generate the receiver-compatible signal.