Abstract: Digital matrices, for example digitized images, are enhanced by comparing a matrix to be enhanced with plural enhancement patterns for each position in the matrix of each element of the matrix to produce pattern codes commensurate with the matches with the enhancement patterns. The pattern codes are employed to generate plural enhancement decisions for each element of the matrix and these enhancement decisions are combined to provide a single enhancement action for each element of the matrix.

Abstract: A television synchronizing signal pattern correction circuit has a change-over switch (23) which can supply a vertical synchronizing signal (V') obtained from an input (13) or from an output (17) of a delay circuit (15). The change-over switch (23) is operated by a signal obtained from an output (31) of a simple measuring circuit (9). With the aid of two pairs of D-flipflops (35, 37; 39, 41), two exclusive-OR gates (43, 45), two AND-gates (47, 49) and a JK-flipflop (52) the measuring circuit (9) measures the mutual location of undelayed (at 11) and delayed (at 19) vertical synchronizing signals with respect to a signal (at 7) having a duty cycle of fifty percent and representing the horizontal synchronizing signals. As a result, unwanted irregularities in the selected vertical synchronizing signal can be avoided, thus making it usable for, inter alia, the synchronization of writing into a field memory.

Abstract: The screen grid of a CRT is connected to a blanking pulse amplifier by means of a resistor and a capacitor. This screen grid is also connected to the anode of a diode. The cathode of the diode is coupled to the ground by means of a ripple-removing capacitor, and is also connected by means of a resistor to the tap of a variable resistor for controlling the screen luminance of the CRT. During each scanning period of the CRT, the diode is turned on, thus equivalently connecting the ripple-removing capacitor to the screen grid. During each blanking period of the CRT, the diode is turned off, thereby disconnecting the ripple-removing capacitor from the screen grid.

Abstract: There is disclosed herein a system for digitally forming synchronization signals. In the preferred embodiment, these synchronization signals are for substitution in place of the original synchronization signals in a television signal. These digitally generated synchronization signals are generated synchronously with the digitization of the video portions of the television signal, and the digitally generated synchronization signals are multiplexed into the stream of digital video data in the appropriate blanking intervals. The system uses a first digital signal number generator to generate a plurality of digital signals which represent the peak amplitudes of the desired synchronization signals. A second digital signal number generator synchronously generates a second plurality of digital signal values representative of the shape of the desired edges for the synchronization signal being generated.

Abstract: The invention relates to a circuit arrangement for a video recorder which derives a line frequency signal from a pulse-shaped oscillator signal by means of a plurality of frequency dividers. The arrangement comprises a first section suitable for VHS or Video-8 video recorders in conformity with the PAL or NTSC standard and a second section adapted to the relevant standard.

Abstract: A method and apparatus for separating sync pulses by charging a capacitor to the sync tip voltage level during occurrence of a sync pulse and discharging the capacitor to the back porch voltage level for an equal duration. The discharge duration is determined by decrementing an up/down counter that was incremented during the sync pulse. A comparator separates the sync pulses by comparing the composite video signal with the voltage on the capacitor.

Abstract: For the synchronized display of MAC signals on a monitor designed to display standard video signals, a decoding device derives synchronizing pulses from the data component of the MAC signal which contains the line-frequency and field-frequency information, and a blanking stage is triggered by the synchronizing pulses for the periodic blanking of a partial segment of the MAC signal to a predetermined constant voltage level in a standard-suitable temporal relationship to the synchronizing pulses.

Abstract: In a picture processing apparatus, a front porch time (FP) conforming to a picture signal from a particular picture input unit (2) is stored beforehand in a register (R) by a host computer (8). When the picture input unit (2) outputs a horizontal synchronizing signal (HSYNC), the front porch time (FP) from issuance of the horizontal synchronizing signal (HSYNC) until the beginning of a significant picture information interval (PCPD) is calculated by referring to the register (R) and counting down the value from the register. The picture information is then introduced into a picture memory (6) from the calculated beginning of the significant picture information interval (PCPD). The picture processing apparatus may be used for a variety of different picture input units, as the host computer stores the front porch time corresponding to the particular picture input unit to be used in the register (R) prior to picture processing.

Abstract: A PLL video detector comprises a phase detector circuit receiving a video intermediate frequency signal and an oscillation output of a VCO for phase-detecting the same. The phase of the oscillation output of the VCO is controlled by a signal obtained by smoothing a detection output of the phase detector circuit by a low-pass filter. In addition, a trap circuit having a center frequency of f.sub.H is provided between the phase detector circuit and the VCO, so that an unecessary component having a frequency of f.sub.H is removed from an output signal of the low-pass filter. Consequently, the VCO stably oscillates, so that occurrence of a buzz sound in a sound output and degradation of the picture quality can be prevented.

Abstract: In one embodiment, the video signal generator outputs a standardized analog video signal. The signal generator includes a clock controlling a sequential address generator. The address generator activates a memory device that is, for example, a ROM. A distortion conditioned standardized digital video signal is stored in the ROM. This distortion conditioned signal has distortion correction characteristics matching an output filter. Following the ROM is a D to A converter that converts the conditioned digital video signal into a conditioned analog video signal. A simple filter follows the D to A converter. The filter introduces distortion into the signal applied at its input but since that signal already has distortion correction characteristics therein, the distortion correction characteristics of the input signal match and substantially cancel the distortion introduced into that signal by the filter. Therefore, a standardized analog video signal is produced at the output of the filter.

Abstract: A clock signal generating circuit for a television receiver, which generates a composite synchronizing signal and a masking signal for controlling the operation of the circuit, the composite synchronizing signal including at least two partial signals.

Abstract: Method and apparatus for in-band, video broadcasting of commands to interactive devices are described. Control data are encoded by subliminally modulating, prior to the remote, composite video broadcast of video program material, a selected sequence of video image fields. The resulting modulated video fields within the viewing area of a television, each having alternately, proportionately raised and lowered luminance horizontal scan lines, are monitored by a light sensitive device positioned adjacent the user's television screen. A semirigid, twisted pair cable connects the device to nearby receiver/transmitter electronics that discriminate the binary data from the program material and amplitude modulate a high frequency infrared (IR) carrier with the data. Interactive devices, e.g.

Abstract: A neighbor image processing device for processing image data according to predetermined program comprises: an address generator for simultaneously generating addresses corresponding to each of a central point and a plurality of individual neighbor points of an image neighbor region; a buffer memory for simultaneously receiving data on the points, and their corresponding addresses from the address generators; a central processor coupled to the address generator and the buffer memory for comparing the neighbor point data with data on the central point of the neighbor region; an arithmetic and logic unit connected to the central processor for selectively modifying the data simultaneously for the individual points according to instructions from the central processor; a data integration unit for receiving a plurality of simultaneous outputs from the arithmetic and logic unit and generating a single output based on instructions from the program; and a decision integrator for receiving a plurality of the single outp

Abstract: A method and apparatus for verifying the proper airing of television programs having a digital identification code recorded on a preselected scan line which is not normally visible to the television viewer. A plurality of television channels are automatically simultaneously monitored by a primary monitoring system at a site 30 within the reception area and broadcast encoded programs are identified and timed and appraised as to their audio and video signal quality. The information generated is stored locally for later comparison with centrally stored 62 information specifying the programs that should have been aired. Each of the channels is sequentially monitored for a preselected fixed time interval, which depends on the number of channels being monitored, under the control of a programmable sequential controller 54. A secondary monitoring system is provided for use as a backup or for monitoring cable channels.

Abstract: A video timing system is provided for clocking an imaging sensor as well as for clocking a downstream video monitor and NTSC encoder. Due to signal processing delays between the sensor and the monitor/encoder, the first pixel is clocked out of the sensor prior to beginning the rasters of the monitor and encoders by a time period which is equal to the signal processing delay. In this manner, the first pixel out of the sensor is displayed at the beginning of the video rasters. In response to a video signal from an external source, the video monitor and NTSC timing is adjusted so as to be synchronous with the external source. Timing adjustment of the sensor is facilitated by the fact that the time period for early clocking of the sensor is unchanged whether or not the external video signal is present.

Abstract: A video stream processing system frame buffer controller for controlling external dynamic random access memory (DRAM) of a frame buffer and interfacing to the video stream processing signal bus. The frame buffer controller has four interfaces, video input interface, video output interface, memory interface and processor interface. The circuit can input image data from a camera and store the frames in external DRAM. The circuit provides for external processor access to pixels in the frame buffer and for output of the frame or portions of the frame, as well as output of frames in a format of CRT display and external DRAM refresh.

Abstract: A video difference key generator has a stored reference video image. An input video image is compared with the reference video image by an absolute difference circuit which substracts corresponding pixels of the two video images, the smaller from the larger, to produce a difference video image. The difference video image may be filtered, and then is input to a transfer function circuit to produce an output which may be used as a key signal for compositing video images.

Abstract: A system and method are disclosed for transmission and reception of high definition television signals. A standard television signal is transmitted over a first transmission frequency channel, and an enhancement signal, to be used for enhancing the standard signal to obtain a high definition signal, is transmitted over a second transmission frequency channel that is non-adjacent to the first transmission frequency channel. A code signal, which identifies the second transmission frequency channel, is combined into the standard television signal before transmission. The code signal is recovered at the receiver, and used to automatically tune the receiver to also receive the enhancement signal sent over the second transmission frequency channel. A second code signal, representative of other information, such as the portion of the second transmission frequency channel that contains the enhancement information, can also be sent with the standard signal.

Abstract: A circuit arrangement for a television receiver including a video text decoder (30), producing signals from the video text data from which control signals for a picture display device can be derived. The circuit arrangement further including a television signal decoder (1), deriving from the television signal via a low-pass filter arrangement (15) the luminance signal which can be taken from the luminance signal output (18). The low-pass filter arrangement (15) has a first attenuation characteristic for suppressing the chrominance signal and a second attenuation characteristic for allowing all video text data to pass. The second attenuation characteristic of the low-pass filter arrangement (15) is used during the period of time in which the video text data occur. The input of the video text decoder (30) is coupled to the luminance signal output (18) of the television signal decoder (1).

Abstract: A method for suppressing the perception of flicker in interlaced video images, includes the steps of: testing, each pixel in an image, for an intensity value below a first predetermined threshold; modifying, for each tested pixel, an intensity value representation for each nearest neighbor pixel along a first axis of said interlaced image having an intensity value exceeding a second predetermined threshold, if the intensity value of the tested pixel is below the first predetermined threshold; displaying, on a video display device, an interlaced image generated by the steps of testing and modifying, having a suppressed perception of flicker.