Patents Examined by Michael Krofcheck
  • Patent number: 10346302
    Abstract: A method for maintaining the coherency of a store coalescing cache and a load cache is disclosed. As a part of the method, responsive to a write-back of an entry from a level one store coalescing cache to a level two cache, the entry is written into the level two cache and into the level one load cache. The writing of the entry into the level two cache and into the level one load cache is executed at the speed of access of the level two cache.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: July 9, 2019
    Assignee: Intel Corporation
    Inventors: Karthikeyan Avudaiyappan, Mohammad Abdallah
  • Patent number: 10324643
    Abstract: A computer implemented method, a computer program product, and a system for automated virtual storage pools within a software-defined storage comprising: receiving a set of physical storage resources that is enabled to have different storage capabilities; receiving a set of applications, wherein each application of the set of applications is enabled to require different storage capabilities; finding most frequently preferred storage capabilities requirements from capabilities of the set of applications; identifying a number of virtual storage pools based on the set of applications; and clustering at least some of the set of physical storage resources into the number of identified virtual storage pools.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: June 18, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Lijun Huang, Jieming Di, Yu Cao, Hui Liu, Devanjan Sarkar
  • Patent number: 10324646
    Abstract: A node controller-based request responding method and node controller, where the method includes receiving, by a first node controller, a first packet, acquiring an information directory, and querying, in the information directory, whether a memory address requested by the first packet is occupied by a second node controller, and when the memory address requested by the first packet is occupied by the second node controller, querying node presence information to determine whether the second node controller exists, and when it is determined that the second node controller does not exist, generating and sending an invalid response packet.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: June 18, 2019
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Gongyi Wang, Ben Chen, Yafei Zhao
  • Patent number: 10318200
    Abstract: A memory system may include: a memory device including a plurality of pages each having a plurality of memory cells coupled to a plurality of word lines and suitable for storing data, and a plurality of memory blocks each having the pages; and a controller suitable for programming test data to a first memory block among the memory blocks before a first time point, and programming meta-data corresponding to the program of the test data to a second memory block among the memory blocks, in case where the memory system including the memory device is changed from a power-on state to a power-off state at the first time point.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: June 11, 2019
    Assignee: SK hynix Inc.
    Inventor: Jong-Min Lee
  • Patent number: 10318209
    Abstract: Discussed herein are methods, devices, and systems for moving a file to a process. A device can include a kernel, a memory, and processing circuitry to: issue one or more move and rename instructions to the memory to change a location and name of a file requested by the second process, issue one or more update access control instructions to update permissions, perform a UAC to determine whether any processes other than the second process currently have the file open and whether any MMaps have the file open, and allow the second process to access the renamed and moved file only if it is determined that no other processes other than the second process have the file open and no MMaps have the file open.
    Type: Grant
    Filed: January 30, 2017
    Date of Patent: June 11, 2019
    Assignee: Forcepoint LLC
    Inventor: Gregory Alan Hildstrom
  • Patent number: 10313769
    Abstract: Technologies for managing partially synchronized writes include a managed node. The managed node is to issue a write request to write a data block, on behalf of a workload, to multiple data storage devices connected to a network, pause execution of the workload, receive an initial acknowledgment associated with one of the multiple data storage devices, wherein the initial acknowledgement is indicative of successful storage of the data block, and resume execution of the workload after receipt of the initial acknowledgement and before receipt of subsequent acknowledgements associated with any of the other data storage devices. Other embodiments are also described and claimed.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: June 4, 2019
    Assignee: Intel Corporation
    Inventor: Steven C. Miller
  • Patent number: 10303607
    Abstract: A dual-server based storage system maintains a first cache and a first non-volatile storage (NVS) in a first server, and a second cache and a second NVS in a second server, where data in the first cache is also written in the second NVS and data in the second cache is also written in the first NVS. In response to a failure of the first server, a determination is made as to whether space exists in the second NVS to accommodate the data stored in the second cache. In response to determining that space exists in the second NVS to accommodate the data stored in the second cache, the data is transferred from the second cache to the second NVS.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: May 28, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kyler A. Anderson, Kevin J. Ash, Lokesh M. Gupta, Matthew J. Kalos
  • Patent number: 10282097
    Abstract: A storage system and method for thin provisioning are provided. In one embodiment, a storage system is provided comprising a memory and a controller. The controller is configured to provide a logical exported capacity of the memory to a host, wherein the logical exported capacity is greater than an actual storage capacity of the memory; receive a command from the host to write data to a logical address; determine whether there is available actual storage capacity in the memory to write the data; and write the data to a physical address in memory that corresponds to the logical address only if it is determined that there is available actual storage capacity in the memory to write the data. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: May 7, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: Amir Shaharabany, Michael Zaidman, Rotem Sela, Hadas Oshinsky
  • Patent number: 10261908
    Abstract: There is provided a method and apparatus of expanding capacity for a cache array. The method includes in response to detecting that a first new cache disk is to be added to a first cache array, initializing the first new cache disk without disabling other cache disks in the first cache array; allocating a storage space for a cache page metadata based on a result of the initializing; storing the cache page metadata into an initialized directory logical unit number, DIR LUN; storing a copy of the cache page metadata from a memory into the DIR LUN to facilitate the first cache disk to be in a ready state; and in response to the first new cache disk being in the ready state, configuring the first new cache disk as being in an initialized state to expand the capacity of the first cache array.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: April 16, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Liam Xiongcheng Li, Xinlei Xu, Lifeng Yang, Huadong Li, Jian Gao
  • Patent number: 10261720
    Abstract: A method for optimizing the use of the non-volatile memory of a motor vehicle computer, used for monitoring a functional member of the vehicle by the computer which is programmed to carry out in the course of a given cycle, during the wake-up thereof, a start-up monitoring stage, and before being put into sleep mode, a shut-down monitoring stage, the computer including a standard counter suitable to be stored in a standard unit and an on-the-fly counter suitable to be stored in an on-the-fly unit, the method including the steps of: incrementing the on-the-fly counter in order to identify a potential malfunction of the monitored functional member; comparing the on-the-fly counter with the standard counter in the course of a next monitoring stage of the computer; and generating information representing a malfunction in the case of detecting a deviation between the counters.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: April 16, 2019
    Assignees: CONTINENTAL AUTOMOTIVE FRANCE, CONTINENTAL AUTOMOTIVE GMBH
    Inventor: Stephane Eloy
  • Patent number: 10255179
    Abstract: A device that provides garbage collection read throttling includes at least one processor that is configured to receive a request to perform a garbage collection read command on one of a plurality of flash memory circuits. The at least one processor is configured to determine whether garbage collection read throttling is enabled, such as when a garbage collection read throttling criterion is satisfied. The at least one processor is configured to buffer the garbage collection read command when garbage collection read throttling is enabled and perform the garbage collection read command when garbage collection read throttling is disabled. When the garbage collection read throttling is enabled and the garbage collection read command is buffered, the at least one processor is configured to perform the buffered garbage collection read command when garbage collection read throttling is subsequently disabled.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: April 9, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: YungLi Ji, Yun-Tzuo Lai, Haining Liu, Ming-Yu Tai
  • Patent number: 10241683
    Abstract: A data processing system includes a backup nonvolatile memory (NVM), a random access memory (RAM), and a controller. The RAM includes a plurality of partitions, each partition having a different corresponding backup frequency. The controller is configured to back up the contents of each partition of the RAM to the backup NVM in accordance with the corresponding backup frequency.
    Type: Grant
    Filed: October 26, 2015
    Date of Patent: March 26, 2019
    Assignee: NXP USA, Inc.
    Inventors: Frank Kelly Baker, Jr., David B. Kramer, Anirban Roy
  • Patent number: 10235099
    Abstract: Provided are a computer program product, system, and method for managing point-in-time copies for extents of data. A point-in-time copy for at least one range of extents in at least one volume for a point-in-time copy identifier is established. Change recording information is generated indicating each of the at least one range of extents less than all of the extents in the at least one volume. An update to data in the at least one range of extents in the point-in-time copy is received and data in the source storage in the at least one range of extents to be updated is copied as changed data to the target storage. Indication is made in the change recording information of the data in the at least one range of extents that has been updated.
    Type: Grant
    Filed: August 18, 2016
    Date of Patent: March 19, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Richard M. Abbott, Theresa M. Brown, Preston A. Carpenter, Ben Esparza
  • Patent number: 10235069
    Abstract: A method and apparatus for accessing a storage device is disclosed. More specifically, for load balancing by dynamically transferring memory address range assignments. In one embodiment, a storage device receives, from a host apparatus, an access request directed at two or more storage addresses, assigns, based on a first storage address of the two or more storage addresses, the access request to a first processor of two or more processors of the storage device, obtains a local memory lock based on the first storage address, determines, based on a second storage address of the two or more storage addresses, that the second storage address is assigned to a second processor of the two or more processors, obtains a remote memory lock from the second processor based on the second storage address and processes the access request.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: March 19, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: Adam Michael Espeseth, Brent William Jacobs
  • Patent number: 10228873
    Abstract: A method for swapping out tape cartridges in tape libraries is disclosed. In one embodiment, such a method includes maintaining, in a tape library, old tape cartridges backing up data in a primary storage system. The method adds, to the tape library, new tape cartridges to replace the old tape cartridges. The method then initiates a data transfer process to move active data to the new tape cartridges. This data transfer process first moves active data in less frequently accessed storage elements, followed by active data in more frequently accessed storage elements. During the data transfer process, the method backs up updates to data in the primary storage system to the new tape cartridges. A corresponding system and computer program product are also disclosed.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: March 12, 2019
    Assignee: International Business Machines Corporation
    Inventors: Joshua J. Crawford, Paul A. Jennas, II, Jason L. Peipelman, Matthew J. Ward
  • Patent number: 10210101
    Abstract: Systems and methods for flushing a cache with modified data are disclosed. Responsive to a request to flush data from a cache with modified data to a next level cache that does not include the cache with modified data, the cache with modified data is accessed using an index and a way and an address associated with the index and the way is secured. Using the address, the cache with modified data is accessed a second time and an entry that is associated with the address is retrieved from the cache with modified data. The entry is placed into a location of the next level cache.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: February 19, 2019
    Assignee: Intel Corporation
    Inventors: Karthikeyan Avudaiyappan, Mohammad Abdallah
  • Patent number: 10198357
    Abstract: A coherent interconnect is provided. The coherent interconnect includes a snoop filter and a circuit that receives a write request, strobe bits, and write data from a central processing unit (CPU); generates a snoop filter request based on the write request; and transmits, at substantially the same time, the snoop filter request to the snoop filter and the write request, the strobe bits, and the write data to a memory controller.
    Type: Grant
    Filed: August 18, 2016
    Date of Patent: February 5, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae Young Hur, Sung Min Hong
  • Patent number: 10198215
    Abstract: A method of writing multi-stream host data to a storage device comprising a CPU, a multi-stream fast release buffer (FRB), and a non-volatile memory (NVM), includes: receiving a command to write the multi-stream host data to the NVM, the multi-stream host data being associated with a logical block number (LBN) and a new stream ID, recording a status of the active stream ID and retrieving a status of the new stream ID to determine a physical address in the NVM for storing one or more codewords (CWs) corresponding to the multi-stream host data, allocating space in a buffer of the FRB for storage of the multi-stream host data, organizing the multi-stream host data into the one or more CWs, and storing the one or more CWs into the allocated space in the buffer, transferring the one or more CWs from the buffer to the physical address in the NVM.
    Type: Grant
    Filed: January 30, 2017
    Date of Patent: February 5, 2019
    Assignee: NGD Systems, Inc.
    Inventors: Vincent Lazo, Joao Alcantara
  • Patent number: 10191666
    Abstract: A method of controlling write parameter selection in a memory device, can include: (i) storing a configuration set number in a configuration register, where the configuration register is accessible by a user via an interface; (ii) receiving a write command from a host via the interface; (iii) comparing the stored configuration set number against set numbers in a register block to determine a match or a mismatch; (iv) downloading configuration bits from a memory array into the register block in response to the mismatch determination; (v) selecting a configuration set corresponding to the stored configuration set number from the register block in response to the match determination; and (vi) using the selected configuration set to perform a write operation on the memory device to execute the write command.
    Type: Grant
    Filed: October 5, 2015
    Date of Patent: January 29, 2019
    Assignee: Adesto Technologies Corporation
    Inventors: Derric Jawaher Herman Lewis, John Dinh, Nathan Gonzales
  • Patent number: 10185506
    Abstract: A method of applying scheduling policies is provided. The method includes distributing user data throughout a plurality of storage nodes through erasure coding, wherein the plurality of storage nodes are housed within a single chassis coupling the storage nodes as a cluster. The method includes receiving operations relating to a non-volatile memory of one of the plurality of storage nodes into a plurality of operation queues. The method includes evaluating each of the operations in the plurality of operation queues as to benefit to the non-volatile solid-state storage according to a plurality of policies. For each channel of a plurality of channels coupling the operation queues to the non-volatile memory, the method includes iterating a selection and an execution of a next operation from the plurality of operation queues, with each next operation having a greater benefit than at least a subset of operations remaining in the operation queues.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: January 22, 2019
    Assignee: Pure Storage, Inc.
    Inventors: John Hayes, Shantanu Gupta, John Davis, Brian Gold, Zhangxi Tan