Patents Examined by Michael Krofcheck
  • Patent number: 11449265
    Abstract: Partitions of drives are used to form a volume of a drive array. Each partition is associated with a trusted computing group (TCG) band. Each drive encrypts data stored on the partition with a key unique to the TCG band. The volume is formed using the partitions of the drives. In response to a band-based erasure being invoked on the volume, each drive of the plurality of drives overwrites the key of the TCG band associated with the partition and provides an erasure certificate attesting to the overwriting of the key. The erasure certifications from the drives are compiled into a consolidated erasure certification that attests to the erasure of the volume.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: September 20, 2022
    Assignee: Seagate Technology LLC
    Inventors: Varun Reddy Boddu, Siew Lian Tay
  • Patent number: 11449226
    Abstract: A drive cluster with RAID (D+P) protection groups initially has D+P=W drives and W partitions. One protection group is created in each partition of the original drive cluster. The original drive cluster is scaled by selecting RAID protection group members starting with a first partition of the new drive and characterized by decrementing drive numbers and incrementing partition numbers, relocating the selected RAID protection group members within partitions such that a selected RAID protection group member on partition X of an existing drive is relocated to partition X of the new drive, and creating a new protection group in vacated partitions and the first partition of the new drive. The scaled drive cluster is split into independent smaller drive clusters when there are at least 2*W drives.
    Type: Grant
    Filed: October 2, 2020
    Date of Patent: September 20, 2022
    Assignee: Dell Products L.P.
    Inventor: Kuolin Hua
  • Patent number: 11442868
    Abstract: A caching system including a first sub-cache and a second sub-cache in parallel with the first sub-cache, wherein the second sub-cache includes: line type bits configured to store an indication that a corresponding cache line of the second sub-cache is configured to store write-miss data, and an eviction controller configured to evict a cache line of the second sub-cache storing write-miss data based on an indication that the cache line has been fully written.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: September 13, 2022
    Assignee: Texas Instruments Incorporated
    Inventors: Naveen Bhoria, Timothy David Anderson, Pete Hippleheuser
  • Patent number: 11416147
    Abstract: A method for protecting data in a storage system is disclosed. In one embodiment, such a method includes detecting, by a first rack power controller, first battery-on status associated with a first uninterruptible power supply. The method further detects, by a second rack power controller, second battery-on status associated with a second uninterruptible power supply. The method communicates, from the first rack power controller to the second rack power controller, the first battery-on status. The method then triggers, by the second rack power controller, a dump of modified data from memory to more persistent storage upon detecting both the first battery-on status and the second battery-on status. A corresponding system and computer program product are also disclosed.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: August 16, 2022
    Assignee: International Business Machines Corporation
    Inventors: Todd C. Sorenson, Brian A. Rinaldi, John C. Elliott, Gary W. Batchelor, Jiwu Duan
  • Patent number: 11403225
    Abstract: A prefetcher, an operating method of the prefetcher, and a processor including the prefetcher are provided. The prefetcher includes a prefetch address generating circuit, an address tracking circuit, and an offset control circuit. The prefetch address generating circuit generates a prefetch address based on first prefetch information and an offset amount. The address tracking circuit stores the prefetch address and a plurality of historical prefetch addresses. When receiving an access address, the offset control circuit updates the offset amount based on second prefetch information, the access address, the prefetch address, and the historical prefetch addresses, and provides the prefetch address generating circuit with the updated offset amount.
    Type: Grant
    Filed: October 20, 2019
    Date of Patent: August 2, 2022
    Assignee: Shanghai Zhaoxin Semiconductor Co., Ltd.
    Inventors: Xianpei Zheng, Zhongmin Chen, Qi Li
  • Patent number: 11397678
    Abstract: Distributed storage nodes having backup power supplies and write-back caching capabilities can be pooled for servicing write requests. For example, a management node of a distributed storage system can determine a subset of storage nodes, from among a group of storage nodes of the distributed storage system, coupled to backup power supplies based on status information received from the group of storage nodes. The status information can indicate whether a respective storage node of the group of storage nodes is coupled to a corresponding backup power supply. The management node can then generate a node pool that includes the subset of storage nodes with write-back caching enabled. The node pool can be configured to perform write-back caching in relation to a write request.
    Type: Grant
    Filed: October 20, 2020
    Date of Patent: July 26, 2022
    Assignee: RED HAT, INC.
    Inventors: Gabriel Zvi BenHanokh, Joshua Durgin
  • Patent number: 11392493
    Abstract: An information handling system includes a non-volatile memory (NVRAM) and a processor. The NVRAM stores a plurality of NVRAM variables and a basic input/output system (BIOS) of the information handling system. The BIOS includes system BIOS variable services. The processor executes the system BIOS variable services. While executing the system BIOS variable services, the processor determines whether a holding area of a first NVRAM variable of the NVRAM variables is completely used. In response to the storage being completely used, the processor calculates a new size of the holding area based on metadata of the first NVRAM variable, and creates a new storage area for the first NVRAM variable. The size of a second holding area of the new storage area equals the new size.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: July 19, 2022
    Assignee: Dell Products L.P.
    Inventors: Balasingh P. Samuel, Vivek Viswanathan Iyer
  • Patent number: 11392496
    Abstract: Provided is a memory management system that efficiently protects data in a cache memory adopting a virtual address cache method. The memory management system includes a cache memory that temporarily stores data for which memory access is requested by a processor core; a state storage unit that stores a security state communicated simultaneously with the memory access request from the processor core; and a memory management unit that manages access to a main memory. In a case where there is a change in the security state when memory access is requested by the processor core, a cache flush is performed for a cache line that hits the request.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: July 19, 2022
    Assignee: SONY CORPORATION
    Inventor: Mamun Kazi
  • Patent number: 11385804
    Abstract: Systems and methods for adding backups to de-duplicated storage and for removing backups from de-duplicated storage are disclosed. Backups can be added to the de-duplicated storage with minimal reference count updates. Backup data sets can be removed without garbage collection processes being performed on the de-duplicated storage.
    Type: Grant
    Filed: August 4, 2020
    Date of Patent: July 12, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Kedar Patwardhan, Anand Ghatnekar
  • Patent number: 11366749
    Abstract: A storage system has a volatile memory, a non-volatile memory, and a controller. The controller of the storage system can implement various mechanisms for improving random read performance. These mechanisms include improved read prediction cache management, using a pattern length for read prediction, and a time-based enhancement for read prediction. Each of these mechanisms can be used alone on in combination with some or all of the other mechanisms.
    Type: Grant
    Filed: February 23, 2021
    Date of Patent: June 21, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Shay Benisty, Ariel Navon, Eran Sharon
  • Patent number: 11366756
    Abstract: A first host device establishes connectivity to a logical storage device of a storage system. The first host device obtains from the storage system host connectivity information identifying at least a second host device that has also established connectivity to the logical storage device, caches one or more extents of the logical storage device in a memory of the first host device, and maintains local cache metadata in the first host device regarding the one or more extents of the logical storage device cached in the memory of the first host device. In conjunction with processing of a write operation of the first host device involving at least one of the one or more cached extents of the logical storage device, the first host device invalidates corresponding entries in the local cache metadata of the first host device and in local cache metadata maintained in the second host device.
    Type: Grant
    Filed: April 13, 2020
    Date of Patent: June 21, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Sanjib Mallick, Vincent H. Westin, Gabriel Benhanokh, Ian Wigmore, Arieh Don
  • Patent number: 11354288
    Abstract: Exemplary methods, apparatuses, and systems include a file system process determining to a flush a node in a first tree. The first node includes a buffer structured as a second tree. The file system process generates an input/output instruction to load the buffer from a first memory to a second memory. The second tree is stored in two more non-contiguous locations in the first memory and the input/output operation includes a read operation corresponding to each of the two or more non-contiguous locations. The file system process causes the input/output instruction to be executed concurrently on the first memory.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: June 7, 2022
    Assignee: VMware, Inc.
    Inventors: Abhishek Gupta, Rob T. Johnson, Srinath Premachandran, Richard P. Spillane, Sandeep Rangaswamy, Jorge Guerra Delgado, Kapil Chowksey, Wenguang Wang
  • Patent number: 11347641
    Abstract: Snapshot metadata may include a plurality of pages of nodes, including active nodes and free nodes. It may be determined whether a snapshot metadata object is eligible for de-allocation, for example, of one or more of the pages of its snapshot metadata nodes. This determination may be based on a number of free nodes in the snapshot metadata object, for example, in relation to the quantity of nodes that are included in a snapshot metadata page. This determination may be made based on previous usage of the nodes allocated to the snapshot metadata object, for example, the number of active nodes relative to a total size of the snapshot metadata object. For example, a maximum extent of active nodes during one or more periods may be compared to a current extent of active nodes to determine whether the snapshot metadata object is eligible.
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: May 31, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Jeffrey Wilson, Michael Ferrari, Shruti Gupta, George F. Lettery
  • Patent number: 11347661
    Abstract: Techniques for transitioning between thread-confined memory segments and shared memory segments are disclosed. The system may instantiate a confined memory segment view. The confined memory segment view confines access to a memory segment to a particular thread. The system may further receive a request to change access permissions for the confined memory segment to allow access by a first set of one or more threads. Responsive to receiving the request to change access permissions for the confined memory segment, the system may instantiate a new memory segment view, wherein the new memory segment view permits access to the memory segment by the first set of one or more threads. The system may also copy metadata from the confined memory segment view to the new memory segment view. The system may de-allocate the memory segment in response to determining that there are no memory segment views associated with the memory segment.
    Type: Grant
    Filed: September 17, 2020
    Date of Patent: May 31, 2022
    Assignee: Oracle International Corporation
    Inventors: Maurizio Cimadamore, James Malcolm Laskey, Jorn Bender Vernee
  • Patent number: 11340826
    Abstract: A solid state drive is provided for improving write consistency when replicating data. The solid state drive includes a plurality of memory die, a host interface, and a memory controller. The memory controller is configured to receive write commands from a host server, update a list of write commands and a status of execution of the write commands to include the write commands from the host server, and write data payloads associated with the write commands to at least a first memory die and a second memory die of the plurality of memory die. In response to the data payloads being written, the memory controller is configured to update the status of execution for the data payloads in the list of write commands and receive an indication that the data payloads have been written to an external device.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: May 24, 2022
    Assignee: Kioxia Corporation
    Inventor: Hubbert Smith
  • Patent number: 11334501
    Abstract: In some examples, a control device includes a controller to receive, from a requester device that is separate from the control device, a request to access a first memory region of a memory. The controller is to determine, based on occurrence of a systems initialization event and according to permissions information that identifies access permissions for respective memory regions of the memory, whether access of content in the first memory region is allowed.
    Type: Grant
    Filed: January 28, 2020
    Date of Patent: May 17, 2022
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Geoffrey Ndu, Ludovic Emmanuel Paul Noel Jacquin
  • Patent number: 11327681
    Abstract: A memory system with at least one namespace includes a memory device and a controller. The memory device includes a plurality of single-level cell (SLC) buffers and a plurality of memory blocks, wherein each memory block includes a plurality of memory cells, each memory cell storing multi-bit data, and is allocated for a respective one of a plurality of zones, wherein each of the at least one namespace is divided by at least some of the plurality of zones. The controller is configured to receive a program request related to at least one application program executed by a host, to determine at least one zone designated by the at least one application program as an open state, and to control the memory device to perform a program operation on at least one memory block allocated for an open state zone.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: May 10, 2022
    Assignee: SK hynix Inc.
    Inventors: Hee Chan Shin, Young Ho Ahn, Yong Seok Oh, Jhu Yeong Jhin
  • Patent number: 11321003
    Abstract: A technique for performing deduplication extends a match found in a digest database by looking forward and/or backward to adjacent data elements. The technique performs data comparisons between data blocks adjacent to a candidate block and corresponding data blocks adjacent to an identified target block. If the data comparisons indicate that an adjacent candidate block matches an adjacent target block, then the adjacent candidate block may be deduplicated to the adjacent target block without having to compute a hash value of the adjacent candidate block or to perform a separate lookup into the digest database.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: May 3, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Uri Shabi, Ronen Gazit
  • Patent number: 11314647
    Abstract: Methods and systems for managing synonyms in VIPT caches are disclosed. A method includes tracking lines of a copied cache using a directory, examining a specified bit of a virtual address that is associated with a load request and determining its status and making an entry in one of a plurality of parts of the directory based on the status of the specified bit of the virtual address that is examined. The method further includes updating one of, and invalidating the other of, a cache line that is associated with the virtual address that is stored in a first index of the copied cache, and a cache line that is associated with a synonym of the virtual address that is stored at a second index of the copied cache, upon receiving a request to update a physical address associated with the virtual address.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: April 26, 2022
    Assignee: INTEL CORPORATION
    Inventor: Karthikeyan Avudaiyappan
  • Patent number: 11314659
    Abstract: Provided are techniques for using real segments and alternate segments in Non-Volatile Storage (NVS). One or more write requests for a track are executed by alternating between storing data in one or more sectors of real segments and one or more sectors of alternate segments for each of the write requests, while setting indicators in a real sector structure and an alternate sector structure. In response to determining that the one or more write requests for the track have completed, the data stored in the one or more sectors of the real segments and in the one or more sectors of the alternate segments are merged to form newly written data. In response to determining that a hardened, previously written data of a track does exist in Non-Volatile Storage (NVS), the newly written data is merged with the hardened, previously written data in the NVS. The merged data is committed.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: April 26, 2022
    Assignee: International Business Machines Corporation
    Inventors: Kyler A. Anderson, Kevin J. Ash, Lokesh M. Gupta, Matthew J. Kalos