Abstract: A caching system including a first sub-cache and a second sub-cache in parallel with the first sub-cache, wherein the second sub-cache includes: line type bits configured to store an indication that a corresponding cache line of the second sub-cache is configured to store write-miss data, and an eviction controller configured to evict a cache line of the second sub-cache storing write-miss data based on an indication that the cache line has been fully written.

Abstract: The subject technologies relate to data processing unit (DPU) accelerated tiering and caching for artificial intelligence (AI) data loading. An example method facilitates DPU-accelerated tiering and caching for AI data loading and includes loading a dataset stored at a first location of a system in response to a request received by a DPU from a host computing environment for access to the dataset, the first location being known to the DPU and not known to the host computing environment, where the dataset is stored at the first location in a first format; storing a transformed dataset, resulting from the DPU transforming the dataset from the first format to a second, different format, at a second location of the system that is different from the first location; and facilitating the access to the transformed dataset by the host computing environment at the second location of the system.

Abstract: A method includes determining a logical saturation of a memory device in a memory sub-system and adjusting a code rate of the memory device based on the logical saturation, wherein the code rate represents a ratio of user data to a combination of the user data and error correction data.

Abstract: An artificial neural network device, including input circuitry configured to provide input data into a neuron, weight operation circuitry configured to input a weight value into the neuron, bias operation circuitry configured to input a bias value into the neuron, activation function circuitry configured to receive an output of the bias operation circuitry and output an activation function output; and a storage device including storage circuitry electrically connected to the weight operation circuitry, the bias operation circuitry, and the activation function circuitry, wherein the input circuitry, the weight operation circuitry, the bias operation circuitry, and the activation function circuitry are operated based on code data, and wherein the storage device includes a plurality of storage portions, each storage portion of the plurality of storage portions configured to store one or more of the code data, the input data, the weight value, the bias value, or the activation function output.

Abstract: A storage device may search for, upon determining that the storage device has entered a preset target state, target setting parameter values, which are values of one or more setting parameters corresponding to a current temperature, in a setting parameter memory. When the search fails, the storage device may reset values of the setting parameters corresponding to the current temperature, and may set an operating environment of the storage device based on the reset values of the setting parameters.

Abstract: Methods, systems, and apparatuses include receiving, by a memory subsystem, a parallel programming command from a host device. A wordline of user data is programmed into a target wordline of a memory portion of a memory device. A duplicate of the wordline of user data is programmed to padding wordlines of the memory portion in parallel with the programming of the target wordline using a command mode.

Abstract: A memory system may include a memory device including a plurality of memory regions and a memory controller configured to control the memory device and allocate some of the plurality of memory regions based on an allocation request of the memory device, the allocation request being provided from an external device. The memory controller is configured to perform a write request provided from the external device to at least one of the allocated memory regions, and monitor a size of written data in the at least one of the allocated memory regions based on the write request. When an error is detected in a first memory region among the allocated memory regions while performing of the write request of the external device, the memory controller is configured to determine whether to maintain the allocation of the first memory region.

Abstract: A method of managing compressed memory includes: receiving a memory command to read compressed data from the compressed memory by decompression thereof by the compressed memory or to write data that is to be compressed and stored by the compressed memory; obtaining, based on the memory command, allocated-state information indicating allocation states of respective slots of the compressed memory; obtaining a slot address of a slot corresponding to the received memory command using bits of a bitmap indicating allocation states of the respective slots and using tags of respective groupings of the bits in the bitmap; translating, based on the obtained slot address, an address for writing or reading the data of the memory command; and compressing or decompressing the data of the memory command based on the translated address.

Abstract: There is provided an apparatus comprising training storage circuitry configured to store training entries, each comprising training data indicative of a trigger memory access request to local storage. The apparatus comprises filter circuitry to generate a filtered sequence of memory access requests by applying a filter to a sequence of memory access requests. The apparatus comprises training circuitry to monitor the filtered sequence, and responsive to observation of the trigger memory access request indicated in a training entry, to update the training data in the training entry. The filter circuitry is configured for each memory access request of the sequence that resulted in a hit on a data item in the local storage, to include the memory access request in the filtered sequence in dependence on a filter criterion independent of a type of request that resulted in the data item being allocated to the local storage.

Abstract: Techniques for optimized file scanning using multi-type volume attachments and sequential block read pre-warming are described. A network-based logical storage volume of a first type providing high input-output operations per second (IOPS) is attached to a compute instance. A prewarmer loads the data of the storage volume by making sequential reads, across a network, of the raw data of the volume. After the prewarming, the logical storage volume attachment type is modified to be of a second type providing comparatively fewer IOPS.

Abstract: The disclosure configures a memory sub-system controller to perform scalable write amplification (WAF) measurement. The controller receives a request to place a memory sub-system into a WAF mode and, in response, reduces a full capacity of the memory sub-system to a reduced capacity by restricting write operations to an individual portion of a set of memory components. The controller generates a log that tracks a number of write operations performed to store data to the individual portion of the set of memory components relative to a plurality of requests to program the data to the individual portion of the memory sub-system. The controller computes, based on the log, the WAF for the full capacity of the memory sub-system based on the WAF of the reduced capacity of the memory sub-system.

Abstract: The described technologies enable a computing device to allocate at least a portion of its persistent memory as volatile memory during runtime. At least some implementations create a file in the persistent memory of the computing device. The file is created in the persistent memory of the computing device during runtime of a virtual machine (VM) hosted by the computing device. The file may be allocated to the VM. The file allocated to the VM may be used as volatile memory. For example, the VM may use the file to store temporary data (e.g., volatile data). In some implementations, the temporary data is associated with an application executing in the VM.

Abstract: In some examples, a memory controller includes a cache and an interface to a communication channel that is connected to a memory module. The memory controller receives an alert based on a counter in the memory module breaching a threshold, where the counter is associated with a row of memory cells in the memory module, and the alert indicates a frequent activation of the row of memory cells. Based on the alert, the memory controller stores, in the cache, data stored in the row of memory cell.

Abstract: Apparatuses and methods for controller signaling of refresh operations. A memory may receive a first or a second type of refresh command. Responsive to the first type of refresh command a first type of refresh operation (e.g., a sequential refresh operation) may be performed. Responsive to the second type of refresh operation a second type of refresh operation (e.g., a targeted refresh operation) may be performed. This may allow the controller to have greater control over the timing of different types of refresh operation in the memory.

Abstract: A system includes memory hardware including a memory and a processing-in-memory (PIM) component. A system includes a host including at least one core. The PIM component includes a memory die (e.g., a dynamic random access memory (DRAM) die) and a base die, e.g., a logic die. The base die includes one or more PIM arithmetic logic units (ALU) and one or more sense amplifiers. In at least some implementations the base die includes a shared static random-access memory (SRAM) cache that is shared between different ALU that reside in the base die.

Abstract: A device may include a first memory media, a second memory media, and at least one control circuit configured to receive placement information for data, store, in a portion of the first memory media, based on the placement information, the data, and store, in a portion of the second memory media, based on the placement information, the data. The at least one control circuit may be configured to receive a request to access, from the portion of the first memory media, the data, and access, based on the request, from the portion of the second memory media, the data. The at least one control circuit may be configured to modify, based on an allocation status, the portion of the first memory media to an available state.

Abstract: A method for locking a rewritable non-volatile memory of an electronic device is described. A first step of initialising the electronic device is performed. At least one memory area of the rewritable non-volatile memory is then selected from a set of N memory areas of the rewritable non-volatile memory, each of the N memory areas having a content, N being an integer ?2. The memory area selected is locked by volatile locking. A second step of initialising the electronic device is performed using a content stored in the memory area selected.

Abstract: Mechanisms, including systems, methods, and media, for processing sub-indirection unit sized data in a solid-state drive (SSD) are provided, the methods including: identifying, in a first portion of storage of the SSD, a plurality of indirection units each containing sub-indirection-unit-sized data and padding; combining the plurality of indirection units into a page-size data structure using a hardware processor; copying contents of the page-sized data structure to a second portion of storage of the SSD; and updating a data structure relating logical address of data to physical locations of data so that an entry corresponding to the sub-indirection-unit-sized data of one of the plurality of indirection units changes from having a physical address in the first portion of storage to having a physical address in the second portion of storage.

Abstract: Systems and methods for managing memory devices are disclosed. A device may include a controller, a first non-volatile memory (NVM) device, and a second NVM device. The controller may be configured to: detect a first condition; set, based on the first condition, the first NVM device for operating in a first operation mode and the second NVM device for operating in a second operation mode; receive a request from a computing device; and select one of the first NVM device or the second NVM device based on the request being respectively one of a first type or a second type, wherein the first NVM device is configured take a first action according to the first operation mode, and the second NVM device is configured take a second action according to the second operation mode.

Abstract: A computing system, preferably including a scratchpad, a plurality of computation units, and a register file, and optionally including a controller. The computing system, or any suitable elements thereof, can optionally be integrated into a processor unit, wherein one or more such processor units can optionally be integrated into a larger-scale computing system. Some or all elements of the larger-scale computing system can be collocated and/or codefined on a single semiconductor chip, can be located and/or defined on separate chips, and/or can be otherwise located and/or defined. A method of operation, preferably including performing computation unit I/O operations and/or performing scratchpad I/O operations. The method of operation is preferably performed using the computing system, but can additionally or alternatively be performed using any other suitable systems.