Abstract: A composable infrastructure module (CIM) with converged functionalities of a network switch, a network interface controller, a software-defined network, a storage virtualisation controller, software-defined storage, redundant array of independent disks (RAID) features, and a composable infrastructure is provided. The CIM includes at least one processor, non-transparent bridge (NTB) devices, an Ethernet switch function, network interface functions, a compose application, and a volume manager module. Each NTB device establishes peripheral component interconnect express (PCIe) connectivity between the processor(s) and multiple nodes and between the nodes, and transfers data therebetween. The Ethernet switch function provides Ethernet connectivity to a spine switch. The volume manager module creates RAID volumes by utilizing storage resources. The compose application selectively pools and extends availability of disaggregated compute, network, and storage resources as direct attached devices on demand.

Abstract: The disclosed computer-implemented method for decentralized address translation can include receiving, by at least one processor implemented outside a processor core, a virtual address translation request. The method can additionally include, retrieving, by the at least one processor and in response to the virtual address translation request, a physical address. The method can also include returning, by the at least one processor, the physical address. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A data storage method, a memory storage device, and a memory control circuit unit are provided. The method includes: receiving at least one write command instructing to store target data from a host system; encoding the target data to generate parity data; and respectively storing the target data and the parity data in a first physical management unit and a second physical management unit, and each of the first physical management unit and the second physical management unit crosses multiple chip enabled (CE) regions. In addition, in the first physical management unit, first data is stored in a first chip enabled region among the chip enabled regions. In the second physical management unit, first parity data for protecting the first data is stored in a second chip enabled region among the chip enabled regions, and the first chip enabled region is different from the second chip enabled region.

Abstract: Provided are a computer program product, system, and method for generating data protection directives to provide to a storage controller to control access to data in cache. A data protection directive is generated for a data subset indicating access request type and a protective action with respect to the access request type for the data subset. The data protection directive is transmitted to the storage controller. The storage controller includes the data protection directive in metadata for the data subset. The data protection directive causes the storage controller to perform the protective action in response to an access request of the access request type to a portion of the data subset.

Abstract: Methods, systems, and devices for host verification for a memory device are described. A memory device may receive a first value from a host device that is associated with an identification of the host device after an event. The memory device may transmit a second value to the host device that is based on the first value and comprises a random set of bits. The memory device may receive from the host device data or a command that comprises an encrypted third value that is based at least in part on the second value and a secret shared between the host device and the memory device. The memory device may also enable a functionality of the memory device based on the encrypted third value.

Abstract: A data processor, such as a graphics processor, is disclosed. The data processor includes a set of one or more counters, and a control circuit that maintains a cache-like pool of corresponding entries. In response to a request for a counter, the control circuit may allocate an entry of the cache-like pool to thereby allocate a counter of the set.

Abstract: A data storage arrangement includes a memory and a controller, where the controller receives an indication of data to be anonymized. The controller further parses a data element to be stored and generates a copy of one or more data portions to be anonymized. The controller further deletes one or more data portions to be anonymized to generate a modified data element to be stored. The controller further generates a copy of the modified data element to be stored utilizing deduplication. The data storage arrangement thus takes in account data anonymization during deduplication (i.e. an anonymization aware deduplication).

Abstract: The application relates to a computing device comprising one or more processors and one or more memory devices having stored thereon computer readable instructions which, when executed by the one or more processors, cause the computing device to establish a storage module for storing a data file. The storage module is configured to: load a data file from a data source into the storage module; compute a hash value of the data file loaded into the storage module and make said hash value available to a hash value consumer; grant read-only access to data consumer(s) for accessing said data file loaded into the storage module. The storage module is further configured to detect any change and/or attempted change of the data file and terminate all data consumers which have been granted access to the data file.

Abstract: A method is described. The method includes performing the following on a flash memory chip: measuring a temperature of the flash memory chip; and, changing a program step size voltage of the flash memory chip because the temperature of the flash memory chip has changed.

Abstract: A non-volatile memory (NVM) system includes a memory array divided into physical pages, control circuitry, and a global transaction log (GTL). Each physical page is configured to store a corresponding payload and corresponding metadata for the physical page. Each entry of the GTL is configured to store a transaction descriptor identifying a transaction and a corresponding physical page used by the transaction. Each entry also has a corresponding transaction log entry (TLE) flag. The control circuitry is configured to populate the entries of the GTL in sequential order with each new transaction, and, in response to completing storing the transaction descriptor for a new transaction, program the corresponding TLE flag by toggling its logic state.

Abstract: A method for memory address mapping in a disaggregated memory system includes receiving an indication of one or more ranges of host physical addresses (HPAs) from a compute node of a plurality of compute nodes, the one or more ranges of HPAs including a plurality of memory addresses corresponding to different allocation slices of the disaggregated memory pool that are allocated to the compute node. The one or more ranges of HPAs are converted into a contiguous range of device physical addresses (DPAs). For each DPA, a target address decoder (TAD) is identified based on a slice identifier and a slice-to-TAD index. Each DPA is mapped to a media-specific physical element of a physical memory unit of the disaggregated memory pool based on the TAD.

Abstract: A method of operating a cache system is disclosed. An update to an entry in one cache of the cache system triggers updates to plural related entries in another cache of the cache system. The entries may be related to each other by virtue of caching data for the same compression block.

Abstract: A data prefetch method includes before data is prefetched, a first data access request that is first obtained, and a data prefetch policy that is determined based on the first data access request and a data lifecycle such that a first data set stored in a second storage medium is stored into a first storage medium according to the data prefetch policy. The first data set includes at least one piece of data, the data prefetch policy includes at least a prefetch length, the data lifecycle indicates duration for storing data in the first storage medium, and a read/write access rate of the second storage medium is less than that of the first storage medium.

Abstract: A host device includes a unit processor configured to generate a near data processing (NDP) request, a host expansion control circuit configured to receive the NDP request; and a local memory device configured to store data corresponding to the NDP request according to control by the expansion control circuit. In response to receiving the NDP request, the host expansion control circuit performs a request processing operation to perform a read or a write operation corresponding to the NDP request on the local memory device and performs a computation operation using the requested data corresponding to the NDP request.

Abstract: A method includes: receiving control data at a first data selector of a plurality of data selectors, in which the control data comprises (i) a configuration registry address specifying a location in a configuration state registry and (ii) configuration data specifying a circuit configuration state of a circuit element of a computational circuit; transferring the control data, from the first data selector, to an entry in a trigger table registry; responsive to a first trigger event occurring, transferring the configuration data to the location in the configuration state registry specified by the configuration registry address; and updating a state of the circuit element based on the configuration data.

Abstract: A storage device may include at least one storage medium, and a controller that may include at least one processor configured to perform an update operation associated with a reclaim unit handle that references at least one reclaim unit of the at least one storage medium, read, based on the update operation, data from a first reclaim unit of the at least one storage medium, and write, based on the update operation, the data to a second reclaim unit of the at least one storage medium. Based on the update operation, the second reclaim unit may be associated with the reclaim unit handle. The first reclaim unit may be associated with the reclaim unit handle. The reclaim unit handle may be a first reclaim unit handle, and the first reclaim unit may be associated with a second reclaim unit handle.

Abstract: Systems, apparatuses, and methods for performing efficient memory accesses for a computing system are disclosed. When a memory controller in a computing system determines a threshold number of memory access requests have not been sent to the memory device in a current mode of a read mode and a write mode, a first cost corresponding to a latency associated with sending remaining requests in either the read queue or the write queue associated with the current mode is determined. If the first cost exceeds the cost of a data bus turnaround, the cost of a data bus turnaround comprising a latency incurred when switching a transmission direction of the data bus from one direction to an opposite direction, then a second cost is determined for sending remaining memory access requests to the memory device. If the second cost does not exceed the cost of the data bus turnaround, then a time for the data bus turnaround is indicated and the current mode of the memory controller is changed.

Abstract: An apparatus for improving the tracking of streams of memory accesses for training a stride prefetcher is provided, comprising a training data structure storing entries for training a stride prefetcher, a given entry specifying: a stride offset, a target address, a program counter address, and a bypass indicator indicating whether a program counter match condition is to be bypassed for the given entry; and training control circuitry to determine whether to update the stride offset for the given entry of the training data structure to specify a current stride between a target address of a current memory access and the target address for the last memory access of the tracked stream, in which the determination by the training control circuitry is controlled to be either dependent on a determination of whether the program counter match condition is satisfied or independent of whether the program counter match condition is satisfied, based on the bypass indicator.

Abstract: A method for managing access to a file based backup (FBB) includes obtaining, by a FBB metadata file operating in a production host, an instant access request for data associated with an FBB, wherein the instant access request is associated with a user, wherein the FBB is associated with a plurality of users comprising the user and a second user, in response to the instant access request: access a FBB metadata file associated with the FBB to determine file data accessible to the user and determining second file data not accessible to the user, wherein the file data is associated with the user, performing an attribute analysis on the FBB metadata file to identify a storage location attributes of the file data and not the second file data, generating a FBB virtual file system, and enabling access to the FBB virtual file system by the user via an application.

Abstract: A recording control system includes a storage medium and a control device that is detachably connectable to and controls reading/writing of data to/from the storage medium. The storage medium stores a first authentication code corresponding to at least one first attribute of the storage medium among attributes regarding reading and writing. The control device includes: a readout unit that outputs first request information to the storage medium to read therefrom at least one common authentication code each corresponding to a respective one of at least one common attribute of the first authentication code and the first request information, the first request information corresponding to at least one second attribute of the control device; an identification unit that identifies the at least one common attribute according to the at least one common authentication code; and a control unit that controls the reading/writing according to the at least one common attribute.