Patents Examined by Michael Krofcheck
  • Patent number: 11112975
    Abstract: Described is a technology by which a virtual hard disk is migrated from a source storage location to a target storage location without needing any shared physical storage, in which a machine may continue to use the virtual hard disk during migration. This facilitates use the virtual hard disk in conjunction with live-migrating a virtual machine. Virtual hard disk migration may occur fully before or after the virtual machine is migrated to the target host, or partially before and partially after virtual machine migration. Background copying, sending of write-through data, and/or servicing read requests may be used in the migration. Also described is throttling data writes and/or data communication to manage the migration of the virtual hard disk.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: September 7, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Dustin L. Green, Jacob K. Oshins, Lars Reuther
  • Patent number: 11112979
    Abstract: Devices, methods, and media are described for runtime memory allocation to avoid defects. One embodiment includes assigning a plurality of memory blocks of a memory sub-system to a plurality of erase groups, such that each erase group of the plurality of erase groups comprises two or more memory blocks of the plurality of memory blocks. A bad block association is determined for each erase group of the plurality of erase groups. Prior to a memory condition being met, memory resources of the memory sub-system are allocated by erase group based on a first set of criteria which are based at least in part on the bad block association for each erase group in order to prioritize use of erase groups with fewer bad blocks.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: September 7, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Woei Chen Peh, Eng Hong Tan, Andrew M. Kowles, Xiaoxin Zou, Zaihas Amri Fahdzan Bin Hasfar
  • Patent number: 11106360
    Abstract: A method, computer program product, and computer system for receiving, by a computing device, an I/O request. It may be identified whether the I/O request is eligible for handling via a first path without also requiring handling via a second path. If the I/O request is eligible, the I/O request may be processed via the first path on a host I/O stack without processing the I/O request via the second path on a storage array I/O stack. If the I/O request is ineligible, the I/O request may be processed via the first path on the host I/O stack and via the second path on the storage array I/O stack.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: August 31, 2021
    Assignee: EMC IP Holding Company, LLC
    Inventors: Adnan Sahin, Michael Scharland, Robert DeCrescenzo, Steven T. McClure, James Marriott Guyer, Jason J. Duquette
  • Patent number: 11086727
    Abstract: Example embodiments relate generally to systems and methods for continuous data protection (CDP) and more specifically to an input and output (I/O) filtering framework and log management system to seek a near-zero recovery point objective (RPO).
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: August 10, 2021
    Assignee: RUBRIK, INC.
    Inventors: Benjamin Travis Meadowcroft, Li Ding, Shaomin Chen, Hardik Vohra, Arijit Banerjee, Abhay Mitra, Kushaagra Goyal, Arnav Gautum Mishra, Samir Rishi Chaudhry, Suman Swaroop, Kunal Sean Munshani, Mudit Malpani
  • Patent number: 11080192
    Abstract: The storage system includes a first partition which is associated with a first processor and in which the first processor temporarily stores data relating to I/O requests processed by the first processor; and a second partition which is associated with a second processor and in which the second processor temporarily stores data relating to I/O requests processed by the second processor. Each processor independently controls the size of the first partition of the first cache memory and the size of the first partition of the second cache memory, and also independently controls the size of the second partition of the first cache memory and the size of the second partition of the second cache memory.
    Type: Grant
    Filed: May 14, 2015
    Date of Patent: August 3, 2021
    Assignee: HITACHI, LTD.
    Inventors: Ryosuke Tatsumi, Shintaro Ito, Masakuni Agetsuma
  • Patent number: 11068179
    Abstract: A smart vehicle system is disclosed, which relates to technology for increasing efficiency of a vehicle-embedded memory. The smart vehicle system includes a host and a storage device. The host selects any one of a first mode and a second mode according to operation, process or workload of a vehicle, and transmits and receives data through different channels in response to the first mode and the second mode. The storage device stores the data received through different channels in the first core circuit and the second core circuit, or reads the data stored in the first core circuit and the second core circuit. The storage device executes different operations in the first mode and the second mode in a manner that an operation to be executed in the first mode is different from an operation to be executed in the second mode.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: July 20, 2021
    Assignee: SK HYNIX INC.
    Inventor: Hyeng Ouk Lee
  • Patent number: 11068199
    Abstract: A method, computer program product, and computing system for associating each data container of a first set of data containers in volatile memory with a metadata page. One or more metadata changes associated with a metadata page may be written to the data container associated with the metadata page. The one or more metadata changes stored in the first set of data containers may be written to a storage array.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: July 20, 2021
    Assignee: EMC IP Holding Company, LLC
    Inventors: Vladimir Shveidel, Ronen Gazit, Uri Shabi, Alex Soukhman
  • Patent number: 11061600
    Abstract: Exemplary methods and apparatus are disclosed to select data evacuation policies for use by a solid state device (SSD) to relocate data from an upper (high performance) memory tier to a lower memory tier. The upper tier may be, e.g., a single-layer cell (SLC) tier of a multi-tier NAND memory, whereas the lower tier may be, e.g., a triple-layer cell (TLC) or a quad-level cell (QLC) tier of the NAND memory. In one example, the SSD monitors its recent input/output (I/O) command history. If a most recent command was a read command, the SSD performs a “lazy” evacuation procedure to evacuate data from the upper tier storage area to the lower tier storage area. Otherwise, the SSD performs a “greedy” or “eager” evacuation procedure to evacuate the data from the upper tier to the lower tier. Other evacuation selection criteria are described herein based, e.g., upon predicting upcoming I/O commands.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: July 13, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Noga Deshe, Gadi Vishne
  • Patent number: 11055220
    Abstract: In a general aspect, a hybrid memory system with cache management is disclosed. In some aspects, a memory access request is transmitted by operation of a host memory controller to a memory module via a memory interface. Whether to execute the memory access request is determined by operation of the memory module according to one or more specifications of the memory interface. In response to determining the memory access request cannot be executed according to the one or more specifications of the memory interface, the host memory controller is notified by the memory module and halted. Respective actions are performed by operation of the memory module based on the memory access request and a type of the memory module.
    Type: Grant
    Filed: August 14, 2020
    Date of Patent: July 6, 2021
    Assignee: Truememorytechnology, LLC
    Inventor: Igor Sharovar
  • Patent number: 11055002
    Abstract: Methods for classifying data in a storage device are provided. A data classifier module in a controller calculates a placement factor of one or more streams of data associated with one or more logical block addresses based on a metadata update and recency count table. The data classifier module then classifies the one or more streams of data associated with one or more logical block addresses as hot, warm, or cold streams of data. Hot streams of data are routed to hot open memory blocks, warm streams of data are routed to warm open memory blocks, and cold streams of data are routed to cold open memory blocks. Routing streams of data to hot, warm, or cold open memory blocks results in more efficient garbage collection procedures and the reduction of block erasures.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: July 6, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Abhijit Rao, Vishwas Saxena
  • Patent number: 11048424
    Abstract: A system includes a storage volume configured to store a data set in a plurality of data blocks, a data store configured to store a plurality of captures of the data set in a plurality of data chunks, and file retrieval logic. The data set includes a file stored in a first data block of the plurality of data blocks. The file retrieval logic is configured to identify a first data chunk of the plurality of data chunks in which the first data block as captured in a first capture is stored in the data store, retrieve the first data chunk from the data store, and read the first data block as captured in the first capture from the first data chunk.
    Type: Grant
    Filed: November 6, 2015
    Date of Patent: June 29, 2021
    Assignee: AMAZON TECHNOLOGIES, INC.
    Inventors: Matthew James Eddey, John Sandeep Yuhan, Mahmood Miah, Abhishek Kumar
  • Patent number: 11030099
    Abstract: A data storage apparatus includes a nonvolatile memory device including a plurality of memory blocks in which a plurality of word lines to which one or more pages are coupled are arranged, a data buffer configured to buffer data to be stored in the one or more pages of the nonvolatile memory device, and a processor configured to detect, when a sudden power off (SPO) occurs, one or more first pages in which an interference has occurred in a memory block in use and store data corresponding to the one or more first pages in which the interference has occurred among the data buffered in the data buffer in a backup memory block of the nonvolatile memory device.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: June 8, 2021
    Assignee: SK hynix Inc.
    Inventors: Seung Gu Ji, Seok Jin Joo
  • Patent number: 11031081
    Abstract: Memories include a controller that, in response to receiving a command to perform an access operation on an array of memory cells, might be configured to perform the access operation on the array of memory cells using trims corresponding to trim settings for the access operation. The controller, in response to receiving a command or a command sequence while performing the access operation that is indicative of a desire to suspend the access operation and load updated trim settings, might be further configured to suspend the access operation, load updated trim settings for the access operation into a particular trim register of a plurality of trim registers, set updated trims for the access operation in response to the updated trim settings in the particular trim register, and resume the access operation using the updated trims.
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: June 8, 2021
    Inventor: Terry Grunzke
  • Patent number: 11024396
    Abstract: Channel information and channel conditions determined by an Offline Tracking process are used to determine whether or not an adjustment to the read reference voltage can be avoided altogether without detrimentally affecting performance, or, alternatively, to determine a precision with which a read reference voltage adjustment should be made. If it is determined based on the channel conditions that a read reference voltage adjustment can be avoided altogether, read performance is improved by reducing the probability that a read reference voltage adjustment needs to be made during normal read operations. If it is determined based on the channel conditions that a read reference voltage adjustment needs to be made with a particular precision, the read reference voltage is so adjusted. This latter approach is advantageous in that relatively fewer adjustments will be made during normal read operations.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: June 1, 2021
    Assignee: seagate technology llc
    Inventors: Zhengang Chen, Erich F. Haratsch, Sundararajan Sankaranarayanan
  • Patent number: 11010083
    Abstract: Various techniques manage a storage system. Such techniques involve: in response to detecting that a first request of a plurality of requests initiated for a bulk request is completed, determining a response time length for the first request, the bulk request being used to migrate data from a first storage device to a second storage device, each request of the plurality of requests being used to read data from the first storage device and write data to the second storage device; determining an average response time length of the completed requests of the plurality of requests based at least in part on the response time length for the first request; and updating the number of the plurality of requests initiated for the bulk request based on the average response time length.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: May 18, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Changyu Feng, Jian Gao, Xinlei Xu, Lifeng Yang, Xiongcheng Li
  • Patent number: 10996949
    Abstract: A method for accessing a binary data vector in a memory unit comprising a plurality of memory banks in which the binary data vector is stored in portions includes receiving a start address of the binary data vector and a power-of-2-stride elements of the data vector and determining offsets, wherein the offsets are determined by applying a plurality of bit-level XOR functions to the start address resulting in a Z vector, using the Z vector for accessing a mapping table, and shifting mapping table access results according to a power-of-2-stride of the binary data vector. Additionally, the method includes determining a sequence of portions of the binary data vector in the n memory banks depending on a binary equivalent value of the Z vector, and accessing the binary data vector in the n memory banks of the memory unit in parallel.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: May 4, 2021
    Assignee: International Business Machines Corporation
    Inventor: Jan Van Lunteren
  • Patent number: 10983915
    Abstract: Systems, apparatuses, and methods for implementing flexible dictionary sharing techniques for caches are disclosed. A set-associative cache includes a dictionary for each data array set. When a cache line is to be allocated in the cache, a cache controller determines to which set a base index of the cache line address maps. Then, a selector unit determines which dictionary of a group of dictionaries stored by those sets neighboring this set would achieve the most compression for the cache line. This dictionary is then selected to compress the cache line. An offset is added to the base index of the cache line to generate a full index in order to map the cache line to the set corresponding to this chosen dictionary. The compressed cache line is stored in this set with the chosen dictionary, and the offset is stored in the corresponding tag array entry.
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: April 20, 2021
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Alexander D. Breslow, John Kalamatianos
  • Patent number: 10964358
    Abstract: The present disclosure includes apparatuses and methods related to scatter/gather in a memory device. An example apparatus comprises a memory device that includes an array of memory cells, sensing circuitry, and a memory controller coupled to one another. The sensing circuitry includes a sense amplifier and a compute component configured to implement logical operations. A channel controller is configured to receive a block of instructions, the block of instructions including individual instructions for at least one of a gather operation and a scatter operation. The channel controller is configured to send individual instructions to the memory device and to control the memory controller such that the at least one of the gather operation and the scatter operation is executed on the memory device based on a corresponding one of the individual instructions.
    Type: Grant
    Filed: August 9, 2019
    Date of Patent: March 30, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Jason T. Zawodny, Kelley D. Dobelstein, Timothy P. Finkbeiner, Richard C. Murphy
  • Patent number: 10956089
    Abstract: An approach is provided in which a storage system detects that an extent residing on a first one of a set of physical storage devices requires relocation. The storage system identifies a set of backend connection properties of each of a set of backend connections between the storage system and the set of physical storage devices. The set of backend connection properties includes at least a connection bandwidth between the storage system and at least one of the physical storage devices. In turn, the storage system relocates the extent from the first physical storage device to a second one of the set of physical storage devices based at least in part, on the set of backend connection properties.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: March 23, 2021
    Assignee: International Business Machines Corporation
    Inventors: Grzegorz Piotr Szczepanik, Kushal Patel, Sarvesh S. Patel, Lukasz Jakub Palus
  • Patent number: 10956088
    Abstract: An approach is provided in which a storage system detects that an extent residing on a first one of a set of physical storage devices requires relocation. The storage system identifies a set of backend connection properties of each of a set of backend connections between the storage system and the set of physical storage devices. The set of backend connection properties includes at least a connection bandwidth between the storage system and at least one of the physical storage devices. In turn, the storage system relocates the extent from the first physical storage device to a second one of the set of physical storage devices based at least in part, on the set of backend connection properties.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: March 23, 2021
    Assignee: International Business Machines Corporation
    Inventors: Grzegorz Piotr Szczepanik, Kushal Patel, Sarvesh S. Patel, Lukasz Jakub Palus