Abstract: In some examples, a memory controller includes a cache and an interface to a communication channel that is connected to a memory module. The memory controller receives an alert based on a counter in the memory module breaching a threshold, where the counter is associated with a row of memory cells in the memory module, and the alert indicates a frequent activation of the row of memory cells. Based on the alert, the memory controller stores, in the cache, data stored in the row of memory cell.

Abstract: Apparatuses and methods for controller signaling of refresh operations. A memory may receive a first or a second type of refresh command. Responsive to the first type of refresh command a first type of refresh operation (e.g., a sequential refresh operation) may be performed. Responsive to the second type of refresh operation a second type of refresh operation (e.g., a targeted refresh operation) may be performed. This may allow the controller to have greater control over the timing of different types of refresh operation in the memory.

Abstract: A system includes memory hardware including a memory and a processing-in-memory (PIM) component. A system includes a host including at least one core. The PIM component includes a memory die (e.g., a dynamic random access memory (DRAM) die) and a base die, e.g., a logic die. The base die includes one or more PIM arithmetic logic units (ALU) and one or more sense amplifiers. In at least some implementations the base die includes a shared static random-access memory (SRAM) cache that is shared between different ALU that reside in the base die.

Abstract: A device may include a first memory media, a second memory media, and at least one control circuit configured to receive placement information for data, store, in a portion of the first memory media, based on the placement information, the data, and store, in a portion of the second memory media, based on the placement information, the data. The at least one control circuit may be configured to receive a request to access, from the portion of the first memory media, the data, and access, based on the request, from the portion of the second memory media, the data. The at least one control circuit may be configured to modify, based on an allocation status, the portion of the first memory media to an available state.

Abstract: A method for locking a rewritable non-volatile memory of an electronic device is described. A first step of initialising the electronic device is performed. At least one memory area of the rewritable non-volatile memory is then selected from a set of N memory areas of the rewritable non-volatile memory, each of the N memory areas having a content, N being an integer ?2. The memory area selected is locked by volatile locking. A second step of initialising the electronic device is performed using a content stored in the memory area selected.

Abstract: Mechanisms, including systems, methods, and media, for processing sub-indirection unit sized data in a solid-state drive (SSD) are provided, the methods including: identifying, in a first portion of storage of the SSD, a plurality of indirection units each containing sub-indirection-unit-sized data and padding; combining the plurality of indirection units into a page-size data structure using a hardware processor; copying contents of the page-sized data structure to a second portion of storage of the SSD; and updating a data structure relating logical address of data to physical locations of data so that an entry corresponding to the sub-indirection-unit-sized data of one of the plurality of indirection units changes from having a physical address in the first portion of storage to having a physical address in the second portion of storage.

Abstract: Systems and methods for managing memory devices are disclosed. A device may include a controller, a first non-volatile memory (NVM) device, and a second NVM device. The controller may be configured to: detect a first condition; set, based on the first condition, the first NVM device for operating in a first operation mode and the second NVM device for operating in a second operation mode; receive a request from a computing device; and select one of the first NVM device or the second NVM device based on the request being respectively one of a first type or a second type, wherein the first NVM device is configured take a first action according to the first operation mode, and the second NVM device is configured take a second action according to the second operation mode.

Abstract: A computing system, preferably including a scratchpad, a plurality of computation units, and a register file, and optionally including a controller. The computing system, or any suitable elements thereof, can optionally be integrated into a processor unit, wherein one or more such processor units can optionally be integrated into a larger-scale computing system. Some or all elements of the larger-scale computing system can be collocated and/or codefined on a single semiconductor chip, can be located and/or defined on separate chips, and/or can be otherwise located and/or defined. A method of operation, preferably including performing computation unit I/O operations and/or performing scratchpad I/O operations. The method of operation is preferably performed using the computing system, but can additionally or alternatively be performed using any other suitable systems.

Abstract: A system can include a processing device operatively coupled with the one or more memory devices, to perform operations that include writing data to the one or more memory devices and performing one or more scan operations on a management unit containing the data to determine a current value of a chosen data state metric. Each scan operation can be performed using a corresponding predetermined read-time parameter value. The operations can include determining whether the current value of the chosen data state metric satisfies a criterion, and can also include, responsive to determining that the current value of the chosen data state metric satisfies the criterion, selecting a remedial operation by determining whether redundancy metadata is included in a fault tolerant data stripe on the one or more memory devices. The operations can also include performing the remedial operation with respect to the management unit.

Abstract: Methods and storage unit allocators for allocating one or more portions of a storage unit to a plurality of tasks for storing at least two types of data. The method includes receiving a request for one or more portions of the storage unit to store a particular type of data of the at least two types of data for a task of the plurality of tasks; associating the request with one of a plurality of virtual partitionings of the storage unit based on one or more characteristics of the request, each virtual partitioning allotting none, one, or more than one portion of the storage unit to each of the at least two types of data; and allocating the requested one or more portions of the storage unit to the task from the none, one, or more than one portion of the storage unit allotted to the particular type of data in the virtual partitioning associated with the request.

Abstract: System and techniques for silent cache line eviction are described herein. A memory device receives a memory operation from a host. The memory operation establishes data and metadata in a cache line of the memory device upon receipt. The metadata is stored in a memory element that corresponds to the cache line. Later, an eviction trigger to evict the cache line is identified. Then, in response to the eviction trigger, current metadata of the cache line is compared with the metadata in the memory element to determine whether the metadata has changed. the cache line can be evicted without writing to backing memory in response to the metadata being unchanged.

Abstract: A memory device supports low power operation by facilitating staggered access to row segments within a row of a memory bank. Upon receiving an activate command to activate a row, the memory device sequentially activates a plurality of local wordlines associated with the row with a stagger interval between activations. Upon receiving an access command associated with the activated row, the memory device sequentially initiates column operations for respective row segments with the same stagger interval between the column operations. The memory device may furthermore facilitate error correction code operations in a staggered manner by sequentially performing computations associated with the different row segments.

Abstract: An example methodology includes, by a computing device, polling a power monitoring device coupled to a storage system for power consumption by the storage system and whether the power consumption exceeds a power consumption threshold. The method also includes, responsive to a determination that the power consumption exceeds the power consumption threshold, managing, by the computing device, the power consumption by the storage system to cause the power consumption to not exceed the power consumption threshold.

Abstract: A method includes error encoding data to produce a plurality of data slices. Metadata is determined for a data slice of the plurality of data slices. The metadata is stored in a metadata storage tree. The data slice is stored in a slice storage location indicated by the metadata. Based on determining to access the data slice, the metadata for the data slice is accessed in the metadata storage tree to determine the slice storage location for the data slice, and the data slice is accessed in the slice storage location based on determining the slice storage location for the data slice via accessing the metadata storage tree.

Abstract: Various example embodiments of a capability for supporting reconfigurable partitioning of high bandwidth memory (HBM) in a multi-processor computing system are presented. The capability for supporting reconfigurable partitioning of HBM in a multi-processor computing system, where the multi-processor computing system includes a multi-processor system-on-chip (SoC) including a set of processors supporting respective sets of processor memory channels and an HBM interconnected via an HBM bus supporting a set of HBM bus channels, may support dynamic mapping of the processor memory channels of the processors of the multi-processor SoC to the HBM bus channels of the HBM, thereby overcoming various limitations of a static mapping of the processor memory channels of the processors of the multi-processor SoC to the HBM bus channels of the HBM.

Abstract: An example device can include at least one network controller configured to receive a data request and to retrieve data based on the data request, and a cache agent configured to receive a data access parameter based on the data request, and reconfigure a cache for at least one memory cache based on the data access parameter. The data request can be received from a computer device and the data can be retrieved from at least one memory device. An example data access parameter can include a latency of at least one network-attached memory device to retrieve data from the at least one memory device based on the data request. An example device can further comprises a flit profiler configured to determine the data access parameter. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: Provided is a device that includes an interface operatively coupled to a locked redundant array of independent disks including M (M>1) memory dice, the M memory dice stores stripes of data, and each stripe spanning over the M memory dice; and control circuitry that performs data compression on data to generate compressed data; stores the compressed data in the stripes; generates parity data of each stripe; determines, for each stripe, memory dice required to store the compressed data; determines, for each stripe, whether the memory dice required to store the compressed data in each stripe is N memory dice or less; where N is an integer less than M; and determines, for each stripe, which stripes will store the parity data of a respective stripe based on the determination of whether the memory dice required to store the compressed data in the respective stripe is N memory dice or less.

Abstract: A processor and an operation method thereof may access a memory in multiple segments. The processor includes a vector register file (VRF) and a load-store device. When the load-store device performs a multi-segment load on the memory, the load-store device reads a plurality of data elements from a source segment of the memory, and then writes the data elements in the VRF within a single write cycle, so that the data elements are written in a same location in different vector registers of the VRF. When the load-store device performs a multi-segment store on the memory, the load-store device reads a plurality of data elements from the VRF within a single read cycle (the data elements are data elements of a same location in different vector registers), and then writes the data elements in a target segment of the memory.

Abstract: Disclosed herein are system, apparatus, article of manufacture, method and/or computer program product embodiments, and/or combinations and sub-combinations thereof, for utilizing a single storage buffer for a dynamic number of players, each using a dynamically sized virtual buffer. For example, a system includes a buffer management controller that receives a request to initiate at least one player instance for displaying a content item. The buffer management controller creates a virtual buffer having a maximum capacity for the player instance. Finally, the buffer management controller identifies one or more available regions of the single storage buffer and maps the virtual buffer to the one or more available regions in response to determining that address space in the one or more available regions matches or exceeds the maximum capacity of the virtual buffer.

Abstract: A storage system includes a NAND storage media and a nonvolatile storage media as a write buffer for the NAND storage media. The write buffer is partitioned, where the partitions are to buffer write data based on a classification of a received write request. Write requests are placed in the write buffer partition with other write requests of the same classification. The partitions have a size at least equal to the size of an erase unit of the NAND storage media. The write buffer flushes a partition once it has an amount of write data equal to the size of the erase unit.