Patents Examined by Michael Krofcheck
  • Patent number: 10168925
    Abstract: Provided are a computer program product, system, and method for generating point-in-time copy commands for extents of data. An establish point-in-time copy command is generated for at least one range of extents in at least one volume in the source storage for a point-in-time copy identifier. The at least one range of extents comprises less than all the extents included in the at least one volume. The establish point-in-time copy command is transmitted to a point-in-time copy manager to cause the point-in-time copy manager to create a point-in-time copy for the copy point-in-time identifier and the at least one range of extents, to generate change recording information indicating each of the at least one range of extents, to copy data in the source storage to be updated as changed data, and to indicate in the change recording information the data that has been updated.
    Type: Grant
    Filed: August 18, 2016
    Date of Patent: January 1, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Richard M. Abbott, Theresa M. Brown, Preston A. Carpenter, Ben Esparza
  • Patent number: 10169148
    Abstract: A method of apportioning storage units in a dispersed storage network (DSN) includes generating storage unit apportioning data indicating a mapping of a plurality of desired numbers of storage units to a plurality of storage sites based on site reliability data. The mapping includes a first desired number of storage units corresponding to a first one of the plurality of storage sites that is greater than a second desired number of storage units corresponding to a second one of the plurality of storage sites in response to the site reliability data indicating that a first reliability score corresponding to the first one of the plurality of storage sites is more favorable than a second reliability score corresponding to the second one of the plurality of storage sites. A plurality of storage units are allocated to the plurality of storage sites based on the storage unit apportioning data.
    Type: Grant
    Filed: August 18, 2016
    Date of Patent: January 1, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Jason K. Resch
  • Patent number: 10162745
    Abstract: Disclosed are system and method for controlling execution of a program. An example method includes determining a memory sector for storing at least a portion of execution instructions of the computer program in virtual memory address space; determining, in the virtual memory address space, one or more pages that contain code instructions and data associated with the memory sector; creating a duplicate of the virtual memory address space comprising the memory sector and the one or more pages; tagging the memory sector and the one or more pages in both the virtual memory address space and its duplicate; receiving a notification to transfer execution of the computer program between different memory sectors while executing instructions stored in either the virtual memory address space or its duplicate; and transferring execution of the computer program to a memory location other than the one in which the notification was received.
    Type: Grant
    Filed: August 11, 2016
    Date of Patent: December 25, 2018
    Assignee: AO Kaspersky Lab
    Inventors: Vladislav V. Pintiysky, Denis V. Anikin, Dmitry A. Kirsanov
  • Patent number: 10162833
    Abstract: The present disclosure provides a method of copying files at a high speed when accesses to both of a local memory physically connected to an access device and a remote memory connected via a wireless network. A file copy controller in the access device generates a FS transfer list in which logical address positions of copy sources and logical address positions of copy destinations are stored, based on file system management information of the local memory and an access list, obtained from another access device, of the remote memory, and inputs the FS transfer list to a non-volatile memory controller connected to the local memory. The non-volatile memory controller copies data between the local memory and the remote memory based on the information stored in the FS transfer list without using a CPU in the access device or an internal bus connected to the CPU.
    Type: Grant
    Filed: June 15, 2015
    Date of Patent: December 25, 2018
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Masayuki Toyama, Takuji Maeda
  • Patent number: 10163502
    Abstract: In one embodiment, a non-volatile memory is controlled in a selectable read mode in response to commands from a processor. Selectable read modes may include a default read memory mode, for example, and a performance read memory mode having a shorter read pulse and a reduced read latency than the default read memory mode, for example. In one embodiment, the performance read memory mode may also have refresh operations at an increased frequency compared to that of the default read mode. Other aspects and advantages are described.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: December 25, 2018
    Assignee: INTEL CORPORATION
    Inventors: Christopher F. Connor, Bruce Querbach, Hanmant P. Belgal
  • Patent number: 10162757
    Abstract: A distributed shared-memory system includes several nodes that each have one or more processor cores, caches, local main memory, and a directory. Each node further includes predictors that use historical memory access information to predict future coherence permission requirements and speculatively initiate coherence operations. In one embodiment, predictors are included at processor cores for monitoring a memory access stream (e.g., historical sequence of memory addresses referenced by a processor core) and predicting addresses of future accesses. In another embodiment, predictors are included at the directory of each node for monitoring memory access traffic and coherence-related activities for individual cache lines to predict future demands for particular cache lines. In other embodiments, predictors are included at both the processor cores and directory of each node.
    Type: Grant
    Filed: December 6, 2016
    Date of Patent: December 25, 2018
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Nuwan Jayasena, Yasuko Eckert
  • Patent number: 10162539
    Abstract: An information processing apparatus includes circuitry that controls mounting or unmounting of a specified storage area to an operating system on the information processing apparatus and a memory that stores a first mount status indicating whether or not mounting or unmounting operation is performed to the information processing apparatus and a second mount status indicating whether or not the specified storage area is mounted. The circuitry presents the specified storage area as an available mounted storage area to a user if the second mount status indicates that the specified storage area is mounted, and does not present the specified storage area as the available storage area if the second mount status indicates that the storage area is not mounted.
    Type: Grant
    Filed: March 17, 2016
    Date of Patent: December 25, 2018
    Assignee: Ricoh Company, Ltd.
    Inventor: Ryosuke Miyahara
  • Patent number: 10156887
    Abstract: Cache memory clock generation circuits for reducing power consumption and read errors in cache memory are provided. In one aspect, a cache memory clock generation circuit employs detector circuit configured to receive a way address and generate a one way hit signal indicating if cache read request results in a single way hit. Clock and enable circuit is configured to generate a cache clock signal in response to a system clock signal and a cache enable signal, and generate a cache read enable signal in response to the cache clock signal and a read enable signal. Gating circuit is configured to generate a read clock signal in response to one way hit signal, cache clock signal, and cache read enable signal. Sense amplifier clock generation circuit is configured to generate sense amplifier clock signal in response to the read clock signal having a defined pulse width.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: December 18, 2018
    Assignee: QUALCOMM Incorporated
    Inventor: Michael Phan
  • Patent number: 10152411
    Abstract: In a method for allocating data to multiple disks for storage, a capability value of each of the multiple disks is obtained. The capability value is ratio of a performance indicator value of a disk to a maximum capacity value of the disk. A greatest capability value is identified from multiple capability value. Based on the greatest capability value and a maximum capacity value of each of the multiple disks, allocation shares of the multiple disks are determined. Based on the determined allocation shares, data is allocated for the multiple disks. Through the method, the overall storage performance of a storage system is improved.
    Type: Grant
    Filed: March 28, 2017
    Date of Patent: December 11, 2018
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Deyu Xia, Huangang Hu, Yao Zhang
  • Patent number: 10152260
    Abstract: An information system according to one embodiment of this invention includes a first computer which is an SDS (Software Defined Storage) having a virtualization function and a second computer which is an SDS. The first computer can provide a logical volume using a volume in the second computer as a storage region by the virtualization function. When the information system receives a direction to install a storage control program to the second computer, the information system specifies the logical volume using the volume of the second computer as the storage region among logical volumes in the first computer, and then moves data stored in the volume of the second computer used by the specified logical volume as the storage region to a storage device in the first computer. Thereafter, the storage control program is installed in the second computer.
    Type: Grant
    Filed: February 16, 2018
    Date of Patent: December 11, 2018
    Assignee: Hitachi, Ltd.
    Inventors: Akira Yamamoto, Takahiro Yamamoto
  • Patent number: 10146787
    Abstract: Techniques and mechanisms described herein facilitate the replication of data between storage nodes. According to various embodiments, a request to provide a data chunk to a target storage node may be received at a source data storage node. A reference data chunk may be identified based on fingerprint information associated with the requested data chunk. The reference data chunk may be stored on the target storage node. The reference data chunk and the requested data chunk may each include a first data portion. Data chunk reconstruction information may be transmitted from the source data storage node to the target data storage node. The data chunk reconstruction information may identify the reference data chunk. The data chunk reconstruction information may include data difference information for constructing the requested data chunk at the target data storage node based on the reference data chunk.
    Type: Grant
    Filed: July 26, 2013
    Date of Patent: December 4, 2018
    Assignee: Quest Software Inc.
    Inventors: Murali Bashyam, Sreekanth Garigala
  • Patent number: 10133665
    Abstract: A method of operating a data storage device includes programming non-fully programmed memory blocks at a point in time when a reference time elapses from a point in time when each of the memory blocks is physically erased, acquiring a first interval and a second interval, calculating a disturb index based on the first interval and the second interval, selecting a victim block for garbage collection based on the disturb index, and copying valid page data of the victim block into a free block. The first interval is defined by a point in time when each of the memory blocks is physically erased and a point in time when each of the memory blocks is fully programmed. The second interval is an interval during which a fully programmed state is maintained after a point in time when each of the memory blocks is fully programmed.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: November 20, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sangkwon Moon, Seung-Yeon Lee, Heewon Lee, In Hwan Doh, NamWook Kang
  • Patent number: 10127156
    Abstract: Techniques provide for specifying priorities and thresholds used for cache promotion and flushing on a per pool basis. The thresholds may include a promotion threshold and a flushing threshold. The promotion threshold is used to determine whether data portions of the pool are promoted to a secondary cache. The flushing threshold is used to determine whether any data portions of the pool currently stored in the secondary cache are flushed to non-volatile physical storage. Each of the promotion threshold and the flushing threshold for the pool may be determined in accordance with the priority specified for the pool. For remaining data portions that are included in a pool for which a pool specific priority is not specified, a default technique may be used, for example, which uses the same promotion threshold and the same flushing threshold for all pools for which a pool specific priority is not specified.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: November 13, 2018
    Assignee: EMC IP Holding Company LLC
    Inventors: Biao Yan, Bo Hu, Jia Huang, Jing Ye, Qian Wu
  • Patent number: 10126973
    Abstract: A system according to certain embodiments associates a signature value corresponding to a data block with one or more data blocks and a reference to the data block to form a signature/data word corresponding to the data block. The system further logically organizes the signature/data words into a plurality of files each comprising at least one signature/data word such that the signature values are embedded in the respective file. The system according to certain embodiments reads a previously stored signature value corresponding to a respective data block for sending from a backup storage system having at least one memory device to a secondary storage system.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: November 13, 2018
    Assignee: Commvault Systems, Inc.
    Inventors: Manoj Kumar Vijayan, Deepak Raghunath Attarde
  • Patent number: 10120583
    Abstract: Several embodiments include a host computer coupled to a solid state drive (SSD). The filesystem of the host computer can receive a write pointer from the firmware of the SSD. The write pointer can reference a next available page to an erase block in the SSD. In response to a file write request to store a target file, the filesystem can determine a logical address range to store at least a portion of the target file based on the file write request and the write pointer. The filesystem can then generate a sector write command to send to the SSD. The sector write command can specify the determined logical address range.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: November 6, 2018
    Assignee: Facebook, Inc.
    Inventor: Song Liu
  • Patent number: 10114748
    Abstract: A method of operating a cache-coherent computing system includes storing first state information corresponding to a first reservation for a first exclusive access to a first memory address requested by a first thread executing on a first processor of a first plurality of processors. The method includes transmitting an output atomic response transaction indicating a status of the first reservation to a coherency interconnection in response to issuance of the first exclusive access to the coherency interconnection. The output atomic response transaction is based on first state information.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: October 30, 2018
    Assignee: NXP USA, Inc.
    Inventor: Sanjay R. Deshpande
  • Patent number: 10108553
    Abstract: A memory management method and device are disclosed. The method includes: managing, by a storage management device, a memory; and when determining that a page table does not include a virtual address carried in a fetch request, managing, by the memory management device, the memory. When determining that the virtual address is valid, the memory management device applies for a blank page. The memory management device is located in a memory controller.
    Type: Grant
    Filed: January 25, 2017
    Date of Patent: October 23, 2018
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Yao Liu, Licheng Chen, Zehan Cui, Mingyu Chen
  • Patent number: 10102131
    Abstract: Methods and mechanisms for improved performance in a system with power management are described. A system includes a data storage device configured to store data and a display control unit configured to retrieve data from the data storage device. The data storage device may be placed in a reduced power state that results in increased latencies for accessing data within the device. The display control unit is configured to monitor an amount of data available for processing within the display control unit. In response to determining the amount of data has fallen to a threshold level, and in anticipation of a forthcoming data access request, the display control unit conveys an indication that prevents the data storage device from entering or remaining in the reduced power state. Subsequently, the display control unit conveys a request for data to the data storage device which will not be in the reduced power state.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: October 16, 2018
    Assignee: Apple Inc.
    Inventors: Gurjeet S. Saund, Peter F. Holland
  • Patent number: 10089226
    Abstract: Systems and methods for immediate physical erasure of data in a memory system in response to a user command are disclosed. In one implementation, a memory system includes a non-volatile memory and a controller in communication with the non-volatile memory. The controller comprises a processor that is configured to receive from a host in communication with the memory system, a destruct command that indicates a user request to make the memory system inoperable. The processor is further configured to perform one or more operations to render the memory system inoperable in response to the destruct command received from the host.
    Type: Grant
    Filed: April 6, 2017
    Date of Patent: October 2, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Konstantin Stelmakh, Gabi Brontvein, Menahem Lasser, Long Cuu Pham
  • Patent number: 10073637
    Abstract: A data storage device includes a nonvolatile memory device; a control unit configured to generate a descriptor in which works for controlling the nonvolatile memory device are written; a memory control unit configured to provide control signals and write data to the nonvolatile memory device based on the descriptor; and a voltage detector configured to provide a voltage drop signal to the memory control unit in the case where a first operating voltage provided to the memory control unit or a second operating voltage provided to the nonvolatile memory device, drops.
    Type: Grant
    Filed: August 18, 2016
    Date of Patent: September 11, 2018
    Assignee: SK Hynix Inc.
    Inventor: Dong Jae Shin