Abstract: Methods and systems for managing synonyms in VIPT caches are disclosed. A method includes tracking lines of a copied cache using a directory, examining a specified bit of a virtual address that is associated with a load request and determining its status and making an entry in one of a plurality of parts of the directory based on the status of the specified bit of the virtual address that is examined. The method further includes updating one of, and invalidating the other of, a cache line that is associated with the virtual address that is stored in a first index of the copied cache, and a cache line that is associated with a synonym of the virtual address that is stored at a second index of the copied cache, upon receiving a request to update a physical address associated with the virtual address.

Abstract: A controller that controls a memory device including a plurality of pages each corresponding to a physical address, the controller may include: a memory suitable for storing a plurality of logical-to-physical (L2P) chunks each indicating mapping between one or more logical addresses and one or more physical addresses and an original valid page bitmap (VPB) indicating whether each of the plurality of pages is a valid page that stores valid data; and a processor suitable for generating a reconstructed VPB based on normal L2P chunks when an corrupted L2P chunk is detected, detecting pages having different states in the original VPB and the reconstructed VPB, obtaining logical addresses mapped to physical addresses of the detected pages, respectively, and recovering the corrupted L2P chunk based on the physical addresses of the detected pages and the obtained logical addresses.

Abstract: Systems, methods and computer-readable memory for garbage collection in a storage device. One method comprises, upon a write of data to a first garbage collection unit (GCU) of the storage device, incrementing a number of logical mapping units stored in the first GCU along with a number of logical mapping units with valid data stored in the first GCU. A number of logical mapping units with invalid data stored in a second GCU is decremented based on the incremented number of logical mapping units with valid data stored in the first GCU. The second GCU is erased when a valid data rate of the second GCU is below a valid data rate of the first GCU.

Abstract: In some examples, a system associates a plurality of buffers in a memory with respective multiple bins of a fingerprint index in persistent storage. The system computes fingerprints for incoming data units, and selects, based on an adaptive sampling indication, a subset of the fingerprints. The system adds fingerprint index entries corresponding to the selected subset of the fingerprints to a respective subset of the multiple bins, wherein adding a fingerprint index entry to a bin of the respective subset of the multiple bins comprises adding the fingerprint index entry to the buffer of the bin.

Abstract: Systems for high performance restore of data to storage devices. A method embodiment commences upon identifying a plurality of virtual disks to be grouped together into one or more consistency sets. Storage I/O commands for the plurality of virtual disks of the consistency sets are captured into multiple levels of backup data. On a time schedule, multiple levels of backup data for the virtual disks are cascaded by processing data from one or more higher granularity levels of backup data to one or more lower granularity levels of backup data. A restore operation can access the multiple levels of backup data to construct a restore set that is consistent to a designated point in time or to a designated state. Multiple staging areas can be maintained using lightweight snapshot data structures that each comprise a series of captured I/Os to be replayed over other datasets to generate a restore set.

Abstract: A method, computer program product, and computing system for receiving content on a high-availability storage system. The content is compared to one or more entries in a static database associated with a cache memory system of the high-availability storage system. If the content does not match the one or more entries in the static database, the content is compared to one or more entries in a dynamic database associated with the cache memory system. If the content does not match the one or more entries in the dynamic database: the content is written to the cache memory system and a representation of the content is written to a temporal database associated with the cache memory system and maintained for a defined period of time.

Abstract: A realm management unit (RMU) maintains an ownership table specifying ownership entries for corresponding memory regions defining ownership attributes specifying, from among a plurality of realms, an owner realm of the corresponding region. Each realm corresponds to at least a portion of at least one software process. The owner realm has a right to exclude other realms from accessing data stored in the corresponding region. Memory access is controlled based on the ownership table. In response to a region fuse command specifying a fuse target address indicative contiguous regions of memory to be fused into a fused group of regions, a region fuse operation updates the ownership table to indicate that the ownership attributes for the fused group of regions are represented by a single ownership entry. This provides architectural support for enabling improvement of TLB performance.

Abstract: Distributed deduplication wherein runtime performance of dedup pipelines in all nodes is monitored. The bottleneck for each pipeline is identified and machine resources from different nodes are reallocated to seek to balance the costs of each stage of each task in each of the pipelines. While the overall cost for each task may remain the same, stalls may be eliminated such that the total cost to complete all the tasks is reduced. The global dedup ratio and the local compression ratio may be used to weight certain stage costs.

Abstract: A processor having a functional slice architecture is divided into a plurality of functional units (“tiles”) organized into a plurality of slices. Each slice is configured to perform specific functions within the processor, which may include memory slices (MEM) for storing operand data, and arithmetic logic slices for performing operations on received operand data. The tiles of the processor are configured to stream operand data across a first dimension, and receive instructions across a second dimension orthogonal to the first dimension. The timing of data and instruction flows are configured such that corresponding data and instructions are received at each tile with a predetermined temporal relationship, allowing operand data to be transmitted between the slices of the processor without any accompanying metadata. Instead, each slice is able to determine what operations to perform on received data based upon the timing at which the data is received.

Abstract: Systems and methods are disclosed comprising receiving a request for a descriptor of a storage system, sending the descriptor to the host including an indication that a component of the storage device is in a restricted operation mode, wherein the host device utilizes the indication to determine a boot mode of the host device.

Abstract: A processor having a functional slice architecture is divided into a plurality of functional units (“tiles”) organized into a plurality of slices. Each slice is configured to perform specific functions within the processor, which may include memory slices (MEM) for storing operand data, and arithmetic logic slices for performing operations on received operand data. The tiles of the processor are configured to stream operand data across a first dimension, and receive instructions across a second dimension orthogonal to the first dimension. The timing of data and instruction flows are configured such that corresponding data and instructions are received at each tile with a predetermined temporal relationship, allowing operand data to be transmitted between the slices of the processor without any accompanying metadata. Instead, each slice is able to determine what operations to perform on received data based upon the timing at which the data is received.

Abstract: A realm management unit (RMU) 20 manages ownership of memory regions by realms, each realm corresponding to at least a portion of a software process executed by processing circuitry. Memory access circuitry 26 enforces ownership rights for the regions, with the owner realm having a right to exclude other realms from accessing data stored within its owned region. The RMU 20 controls transitions of memory regions between region states, including an invalid state 220, a valid state 222, and a scrub-commit state 800 in which the memory region is allocated to an owner realm, inaccessible to that owner realm until a scrubbing process has been performed for the memory region to set each storage location of the region to a value uncorrelated with a previous value stored in the storage location, and prevented from being reallocated to a different owner realm.

Abstract: An apparatus having memory dies with a memory cell array divided into a plurality of data segments. A stagger circuit selects a common command signal and sets a column access signal to select a data segment to be accessed based on the common command signal and/or an individual command signal to perform a memory operation corresponding to the selected common command signal on the selected data segment. A data bus connects the memory cell arrays to form data units with each data unit including a data segment from each memory cell array and configured such that the data segments are connected in parallel to the data bus and use a same line of the data bus. The stagger circuits are configured such that data segments identified for activation in the plurality of memory dies are not part of a same data unit.

Abstract: According to one embodiment, a data storage apparatus includes a controller with a data protection function. The controller manages first and second personal identification data. The first personal identification data only includes authority to request inactivation of the data protection function. The second personal identification data includes authority to request inactivation of the data protection function and activation of the data protection function. The controller permits setting of the first personal identification data, when the second personal identification data is used for successful authentication and the first personal identification data is an initial value, or when the data protection function is in an inactive state.

Abstract: The described technology is generally directed towards mapping doubly mapped storage clusters to resources of a real storage cluster in a way that provides high performance. In one aspect, the doubly mapped storage clusters are divided into logical columns, with each logical column corresponding to a doubly mapped node, and having a column height corresponding to a number of storage resources (e.g., disks multiplied by disk extents) managed by that doubly mapped node. The columns are logically positioned within a logical profile having dimensions of the real storage cluster. For example, the logical columns can be selected based on column height, and placed in the logical profile based on free disk extents of the nodes, greatest number of free disk extents first. Once logically positioned, the logical columns in the logical rectangle establish the mapping (e.g., embodied in a mapping table) that results in high performance.

Abstract: According to various embodiments, systems and methods are provided that relate to shared access to Storage Area Networks (SAN) devices. In one embodiment, a Storage Area Network (SAN) host is provided, comprising: a server component: a first host bus adapter configured to be connected to a SAN client over a first SAN; a second host bus adapter configured to be connected to a SAN storage device over a second SAN; and wherein the server component is configured to manage a data block on the SAN storage device, receive a storage operation request from the SAN client through the first host bus adapter, and in response to the storage operation request, perform a storage operation on the data block, the storage operation being performed over the second SAN through the second host bus adapter.

Abstract: Transferring data between a first storage device coupled to a host computing system and a second storage device coupled to the first storage device includes the first storage device receiving a command from the host computing system, the first storage device determining if the command is an out-of-band (OOB) storage command, and, if the command is an OOB storage command, the first storage device sending a command to the second storage device to cause data to be transferred directly between the first storage device and the second storage device independent of the host computing system. Transferring data between a first storage device coupled to a host computing system and a second storage device coupled to the first storage device may also include the first storage device emulating a host computing system in connection with communicating with the second storage device. The second storage device may be a tape emulation unit.

Abstract: Disclosed are an electronic device and a data compression method thereof. According to a data compression method of an electronic device of the present invention, the method comprises the steps of: compressing a page; determining whether data included in the compressed page is stored in a memory; and merging the compressed page with data previously stored in the memory when a result of the determination shows that the data included in the compressed page is the same as the previously stored data. Therefore, the electronic device can prevent a page including the same or similar data from being stored a multiple number of times in a swap area, thereby raising memory securing efficiency.

Abstract: A method for memory address mapping in a disaggregated memory system includes receiving an indication of one or more ranges of host physical addresses (HPAs) from a compute node of a plurality of compute nodes, the one or more ranges of HPAs including a plurality of memory addresses corresponding to different allocation slices of the disaggregated memory pool that are allocated to the compute node. The one or more ranges of HPAs are converted into a contiguous range of device physical addresses (DPAs). For each DPA, a target address decoder (TAD) is identified based on a slice identifier and a slice-to-TAD index. Each DPA is mapped to a media-specific physical element of a physical memory unit of the disaggregated memory pool based on the TAD.

Abstract: A memory controller controls a memory device including a plurality of memory cells. The memory controller may include a workload determination circuit configured to determine a workload state indicating an operating pattern of the memory device based on optimal read voltages for reading the plurality of memory cells when a read operation performed on the memory cells fails; and an operating environment setting circuit configured to set an operating environment of the memory device based on the workload state.