Patents Examined by Michael Maskulinski
  • Patent number: 11048597
    Abstract: Exemplary methods, apparatuses, and systems include a controller detecting a trigger to configure a memory. The memory includes a plurality of dice, including two or more spare dice. The controller accesses each die via one of a plurality of channels. The controller accesses a first spare die via a first channel and the second spare die via a second channel. In response to detecting the trigger, the controller maps a plurality of logical units to the plurality of dice, excluding the two spare dice. The mapping includes mapping each logical unit of the plurality of logical units across multiple dice of the plurality of dice, such that a first half of the plurality of logical units reside on dice accessible via channels other than the first channel and a second half of the plurality of logical units reside on dice accessible via channels other than the second channel.
    Type: Grant
    Filed: May 14, 2018
    Date of Patent: June 29, 2021
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Justin Eno, Samuel E. Bradshaw
  • Patent number: 11043967
    Abstract: A method is provided for channel encoding in a communication system using an LDPC code. The method includes encoding input bits using a BCH code, shortening bits of the encoded input bits according to a number of bit groups to be shortened and an order among a plurality of orders according to which the bit groups are shortened, wherein the number of bit groups to be shortened is based on a number of bits to be shortened, which is based on a number of the encoded input bits, encoding information bits including the encoded input bits and the shortened one or more bits, using an LDPC code to generate parity bits, puncturing bits in the parity bits based on a puncturing parameter among puncturing parameters, and transmitting a signal generated from the encoded information bits based on the punctured bits. The plurality of orders being based on the puncturing parameters and including first and second orders.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: June 22, 2021
    Inventors: Se-Ho Myung, Hong-Sil Jeong, Sung-Ryul Yun, Jae-Yoel Kim, Hyun-Koo Yang, Hak-Ju Lee, Jin-Hee Jeong
  • Patent number: 11036271
    Abstract: Methods and systems are provided performed by a computing system is provided for determining reserve power for power supply elements in a power distribution system. A method determines the non-failure power supplied by each power panel. The non-failure power is the power supplied during normal operation, that is when no panel fails. Then, for each panel, the method designates that panel as failed and determines a failure power supplied by each panel assuming that the designated panel has failed. For each panel, the method also determines a maximum failure power supplied by that panel and sets a reserve power for that panel to the difference between the maximum failure power and the non-failure power for that panel.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: June 15, 2021
    Assignee: Server Farm Realty, LLC
    Inventor: David Eastman
  • Patent number: 11036597
    Abstract: A semiconductor memory system includes a memory medium and a data input/output (I/O) pin repair control circuit. The memory medium includes a plurality of memory dies and a spare die. Each of the plurality of memory dies has a plurality of memory regions and a plurality of data I/O pins, and the spare die has a plurality of spare regions and a plurality of data I/O pins. The data I/O pin repair control circuit performs a repair process for replacing an abnormal data I/O pin among the plurality of data I/O pins included in any of the plurality of memory dies with a data I/O pin of the plurality of data I/O pins included in the spare die.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: June 15, 2021
    Assignee: SK hynix Inc.
    Inventors: Wongyu Shin, Jung Hyun Kwon, Seunggyu Jeong, Do Sun Hong
  • Patent number: 11030061
    Abstract: Techniques are provided for overcoming failures in a memory. One portion of the memory may operate in a single chip spare mode. Upon detection of an error in a single chip in the portion of the memory, a region of the portion of the memory may be converted to operate in a double chip spare mode. The memory may be accessed in both single and double chip spare modes.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: June 8, 2021
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Gary Gostin, Erin A. Handgen
  • Patent number: 11017875
    Abstract: Tracking address ranges for computer memory errors including detecting, by memory logic, an error at a memory address, the memory address representing one or more memory cells at a physical location of computer memory; reporting, by the memory logic to memory firmware, the detected error including providing the memory firmware with the memory address; identifying, by the memory firmware, an address range affected by the detected error including scanning the computer memory in dependence upon the memory address; determining, by the memory firmware, a region size based on the address range affected by the detected error; and populating an entry in a mark table corresponding to the detected error, including populating a field specifying the region size and a field specifying a match address corresponding to the memory address.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: May 25, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John S. Dodson, Marc A. Gollub, Warren E. Maule, Brad W. Michael
  • Patent number: 11016836
    Abstract: Disclosed are systems, methods and non-transitory computer-readable mediums for dynamically presenting and updating a directed time graph displayed in a graphical user interface. In some examples, the method can include displaying a suggested path within a graphical user interface on a computer screen, the suggested path can include outstanding issues of elements of a network. The displaying the suggested path can include determining based on one or more factors an efficient ordering of the outstanding issues and ordering the outstanding issues based on the one or more factors. The method can also include monitoring, at regular intervals, updates to the one or more outstanding issues and automatically updating the suggested path, by a processor, based on the updates to the one or more outstanding issues.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: May 25, 2021
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Jay Kemper Johnston, Magnus Mortensen, David C. White, Jr., Joseph Michael Clarke
  • Patent number: 11010251
    Abstract: At least one processing device is configured to detect a failure event impacting at least a first storage node of a distributed storage system, and responsive to the detected failure event, to initiate a metadata recovery process for at least the first storage node. In conjunction with the metadata recovery process, destaging of a metadata update journal of the first storage node is performed, the destaging of the metadata update journal of the first storage node being performed in multiple phases, including at least a preload phase in which, for each of a plurality of pages required for the destaging of the metadata update journal, one or more address locks are obtained for the page, the page is preloaded into a memory of the first storage node from persistent storage accessible to the first storage node, and the one or more address locks are released, and an update and write phase.
    Type: Grant
    Filed: March 10, 2020
    Date of Patent: May 18, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Alex Soukhman, Lior Kamran
  • Patent number: 11010262
    Abstract: Technologies are described for facilitating database system recovery in a distributed database environment having a master node and at least one slave node. The at least one slave node receives a preliminary slave log backup position. The at least one slave node replays at least a portion of one or more log backups until the preliminary log backup position is reached. The at least one slave node receives a final slave log backup position. The slave node replays at least a portion of one or more log backups until the final slave log backup position is reached.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: May 18, 2021
    Assignee: SAP SE
    Inventor: Martin Brunzema
  • Patent number: 11010264
    Abstract: A first server in, for example, a primary datacenter, may be paired with a second server in, for example, a backup datacenter. The first server may include a first datastore, which includes a plurality of virtual machines, and the second server may include a second datastore. The first and second datastores may then be mapped to each other. The plurality of virtual machines included in the first datastore are then, without any user prompting, replicated at the second datastore. Therefore, when the first server becomes unavailable, the virtual machines included in the first datastore may still be accessible at the second server.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: May 18, 2021
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Sudarsana Rao Piduri, Swapnil Sham Daingade
  • Patent number: 10997059
    Abstract: There is provided a computer-implemented method of testing an application. The method, responsive to first mark data being included in second mark data, obtains second temporary test scripts for testing at least one test case of the second version of the application, wherein the second temporary test scripts being recorded with the second mark data. The method obtains a second correspondence between increased test data and increased data in the second mark data compared with the first mark data. The method substitutes the test data and the increased test data for the second mark data in the second temporary test scripts based on both the first and second correspondences to obtain second test scripts for testing the at least one test case of the second version of the application.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: May 4, 2021
    Assignee: International Business Machines Corporation
    Inventor: Ang Yi
  • Patent number: 10990462
    Abstract: Disclosed herein are various embodiments that perform application-aware input/output (I/O) fencing operations, certain of which embodiments include, in response to detection of a network partition event in a cluster, determining a first application weight, determining whether the first one or more application instances should be delayed in a cumulative fencing race, performing the cumulative fencing race (in response to a determination that the first one or more application instances should be delayed in the cumulative fencing race), and performing the cumulative fencing race without introducing the delay with regard to the first one or more application instances (in response to a determination that the first one or more application instances should not be delayed in the cumulative fencing race).
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: April 27, 2021
    Assignee: Veritas Technologies LLC
    Inventors: Jai Gahlot, Abhijit Toley
  • Patent number: 10990488
    Abstract: While the management module of an information handling system is set as a standby module, an enclosure controller provides first requests for attribute data of the information handling system, and receives and stores first response data for attribute data associated with a first subset of the first requests in a local memory of the enclosure controller. The enclosure controller receives request failure responses associated with a second subset of the first requests directed to a subset of the attributes data for the information handling system stored in a shared memory. While the management module is set as an active module, the management module is granted access to the shared memory. The enclosure controller provides retry requests for attributes associated with the request failure responses, and receives and stores second response data associated with the retry requests in the local memory.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: April 27, 2021
    Assignee: Dell Products L.P.
    Inventors: Michael E. Brown, Joshua M. Pennell, Henry Pang
  • Patent number: 10983876
    Abstract: A system including a plurality of nodes. Each node includes a pending operations list, an unstable operations list, and a hardware controller. The pending operations list can include operations that have not yet been executed on the node. The unstable operations list can include operations that have not yet been stored on non-volatile data storage. Each of the operations listed in the unstable operations list can include a listing of all other operations that must be executed prior to the operation being executed on each respective node. The hardware controller can be configured to execute at least one operation listed in the pending operations list, remove at least one executed operation from the pending operations list, and remove at least one operation from the unstable operations list.
    Type: Grant
    Filed: October 19, 2018
    Date of Patent: April 20, 2021
    Assignee: Seagate Technology LLC
    Inventor: Nikita Danilov
  • Patent number: 10977144
    Abstract: A memory system includes: a nonvolatile memory device including a plurality of memory blocks and spare blocks; and a memory controller configured to control the nonvolatile memory device. The nonvolatile memory device may store spare information to any one block of the memory blocks or the spare blocks. When a bad block is detected from the memory blocks, the nonvolatile memory device replaces the bad block with any one of the spare blocks according to the spare information.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: April 13, 2021
    Assignee: SK hynix Inc.
    Inventors: Chi Eun Kim, Soo Nyun Kim
  • Patent number: 10970148
    Abstract: Embodiments of the present disclosure provide a method, device and computer program product for managing an input/output (I/O) stack. The method comprises obtaining metadata related to an I/O request stored in the I/O stack, the metadata at least comprising a timestamp when the I/O request is placed in the I/O stack; determining, based on the timestamp, a length of time during which the I/O request waits for processing; and in response to the length of time exceeding a threshold time length, performing a predetermined operation on the I/O request to prevent the I/O stack from being congested.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: April 6, 2021
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Bing Liu, Man Lv
  • Patent number: 10956287
    Abstract: Provided are techniques for implementing shared Ethernet adapter (SEA) failover, including receiving a first ARP packet at a first SEA coupled to a first switch; parsing, by the first SEA, a first MAC address and VLAN ID (VID) corresponding to the first ARP packet; transmitting the first MAC address and VID to a second SEA coupled to a second switch; detecting the first SEA has transitioned from a primary configuration to an inactive configuration and the second SEA has transitioned from a backup configuration to the primary configuration; and responsive to the detecting, transmitting a reverse ARP packet to the second switch notifying the second switch that the first SEA has transitioned to an inactive configuration and that the second SEA has transitioned to an active configuration; and configuring the first switch to forward any subsequent packets to the second switch rather than the first SEA.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: March 23, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Juliet M. Kim
  • Patent number: 10949277
    Abstract: Provided are a computer program product for managing bus interface errors in a storage system coupled to a host and storage. A determination is made as to whether a first number of correctable errors on a first bus interface, connecting a first processing unit to the storage, exceeds a second number of correctable errors on a second bus interface, connecting a second processing unit to the storage, by a difference threshold. The correctable errors in the first and second bus interfaces are detected and corrected in the first and second bus interfaces by first hardware and second hardware, respectively. In response to determining that the first number of correctable errors exceeds the second number of correctable errors by the difference threshold, at least a portion of Input/Output (I/O) requests are redirected to a second processing unit using the second bus interface to connect to the storage.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: March 16, 2021
    Assignee: International Business Machines Corporation
    Inventors: Matthew G. Borlick, Lokesh M. Gupta, Trung N. Nguyen
  • Patent number: 10929220
    Abstract: Methods and systems for detecting and correcting anomalous behavior include generating a joint binary embedding of each of a set of historical time series sequences. A joint binary embedding of a recent time series sequence is generated. A ranked list of the plurality of historical time series sequences is generated according to respective similarities of each historical time series sequence to the recent time series sequence based on the respective joint binary embeddings of each. Anomalous behavior of a system associated with the recent time series sequence is determined according to a label of a top-ranked historical time series sequence in the ranked list. A corrective action is performed to correct the anomalous behavior.
    Type: Grant
    Filed: January 11, 2019
    Date of Patent: February 23, 2021
    Inventors: Dongjin Song, Ning Xia, Haifeng Chen
  • Patent number: 10929230
    Abstract: Techniques manage a storage system. The storage system includes at least one part of multiple storage devices, here respective storage devices among the multiple storage devices include a first portion and a second portion, the first portion is for storing data and the second portion is reserved for rebuilding the storage system. The techniques involve: determining a storage device in the at least one part of storage devices fails; recovering data in a first portion of the failed storage device on the basis of data in a first portion of a normal storage device other than the failed storage device in the at least part of storage devices; selecting a group of storage devices from normal storage devices among the multiple storage devices; and writing recovered data to a second portion in the group of selected storage devices. Thereby, the speed of rebuilding the storage system may be increased, and further the overall performance of the storage system may be enhanced.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: February 23, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Jian Gao, Jibing Dong, Xinlei Xu, Geng Han, Jianbin Kang