Patents Examined by Michael Maskulinski
  • Patent number: 10445165
    Abstract: Examples associated with inactive application restarting are described. One example method includes establishing a connection between a host device and a remote device. The connection is used for communications between the host device and an application on the remote device. An inactive state of the application is detected on the remote device. A message is transmitted to the remote device to notify a user to restart the application. A user interaction with the message restarts the application.
    Type: Grant
    Filed: August 21, 2017
    Date of Patent: October 15, 2019
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Chee Keat Fong, Phuc Dinh
  • Patent number: 10445194
    Abstract: A memory system may include: a memory device including a plurality of memory blocks each memory block having a plurality of pages; and a controller suitable for performing a program operation of storing data segments and meta segments in the pages, and recording a checkpoint information for the program operation in the pages.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: October 15, 2019
    Assignee: SK hynix Inc.
    Inventor: Jong-Min Lee
  • Patent number: 10437686
    Abstract: To eliminate additional development for monolithic applications, the high availability services are externalized from the application and performed by an agent executing alongside an application on a server or computing device. The agent is provided resources for verifying that an application is active and for controlling the application. The agent can use the provided resources to initialize a failover instance of the application as needed. Additionally, the agent can communicate and broadcast the status of its monitored application(s) to other agents through a shared database so that an agent on another server can initialize a failover instance of the application as needed. The agent can synchronize configuration files among the one or more instances of an application so that the application executes uniformly across all instances. The file synchronization is performed externally from the application and does not require additional development or modification of the existing monolithic application.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: October 8, 2019
    Assignee: CA, Inc.
    Inventors: Yang Yang, Patricia Ann Harasta
  • Patent number: 10430304
    Abstract: Described herein are methods, systems, and software for accommodating failover of a content node in a content delivery network. In one example, a method of operating a control node includes receiving content requests issued by end user devices. The method further provides, for at least a first content request, mapping a first connection between a first end user device and a first content node, the first connection defined by at least a network address of the first end user device and a virtual next hop network address, and directing traffic associated with the first connection to the first content node using at least the virtual next hop network address. The method also includes identifying a service interruption associated with the first content node and, responsive to the service interruption, identifying a second content node to handle the communications for the first connection.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: October 1, 2019
    Assignee: Fastly, Inc.
    Inventor: João Diogo Taveira Araújo
  • Patent number: 10430301
    Abstract: Provided is a processor system including a first processor driven by a first driving voltage and a first driving clock, a second processor driven by a second driving voltage and a second driving clock and configured to perform an identical task to the first processor, and a defect detector configured to perform level synchronization or clock domain synchronization on a first output signal provided from the first processor and a second output signal provided from the second processor to compare the first and second output signals, wherein the first and second driving voltages are respectively provided from mutually independent power supply sources and the first and second driving clocks are respectively provided from mutually independent clock generators.
    Type: Grant
    Filed: February 14, 2017
    Date of Patent: October 1, 2019
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Young-Su Kwon, Kyung Jin Byun, Nak Woong Eum
  • Patent number: 10430264
    Abstract: Provided are a computer program product for managing bus interface errors in a storage system coupled to a host and storage. A determination is made as to whether a first number of correctable errors on a first bus interface, connecting a first processing unit to the storage, exceeds a second number of correctable errors on a second bus interface, connecting a second processing unit to the storage, by a difference threshold. The correctable errors in the first and second bus interfaces are detected and corrected in the first and second bus interfaces by first hardware and second hardware, respectively. In response to determining that the first number of correctable errors exceeds the second number of correctable errors by the difference threshold, at least a portion of Input/Output (I/O) requests are redirected to a second processing unit using the second bus interface to connect to the storage.
    Type: Grant
    Filed: June 2, 2017
    Date of Patent: October 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Matthew G. Borlick, Lokesh M. Gupta, Trung N. Nguyen
  • Patent number: 10423788
    Abstract: Methods, media, and systems for detecting an anomalous sequence of function calls are provided. The methods can include compressing a sequence of function calls made by the execution of a program using a compression model; and determining the presence of an anomalous sequence of function calls in the sequence of function calls based on the extent to which the sequence of function calls is compressed. The methods can further include executing at least one known program; observing at least one sequence of function calls made by the execution of the at least one known program; assigning each type of function call in the at least one sequence of function calls made by the at least one known program a unique identifier; and creating at least part of the compression model by recording at least one sequence of unique identifiers.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: September 24, 2019
    Assignee: The Trustees of Columbia University in the City of New York
    Inventors: Angelos D. Keromytis, Salvatore J. Stolfo
  • Patent number: 10409682
    Abstract: The technology disclosed herein includes a method for dividing a body of user data into a plurality of data blocks, and writing the plurality of data blocks into chunk zones in parallel streams, the chunk zones located in a first ordered pool of storage devices. In some implementations, the method includes adding additional storage devices to the first ordered pool making a second ordered pool, including the first ordered pool, and writing the plurality of data blocks across the second ordered pool of storage devices, such that each of the storage devices including spare capacity. The method includes determining if a storage device fails, and seeking data for the data blocks on the failed storage device from of the other storage devices.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: September 10, 2019
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Ian Davies, Ruiling Luo, Thomas George Wicklund, Kenneth F. Day, Douglas William Dewey
  • Patent number: 10409700
    Abstract: A method is provided to get a high test coverage through a large number of test cases with a minimum number of test programs. Tests are performed flexibly in various environments, using parameters in multiple dimensions. The parameters can be dynamically extracted from the machine or simulator either by controlling scripts or by the test program itself. Multiple ways are offered to execute subsets of the test combinations.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: September 10, 2019
    Assignee: International Business Machines Corporation
    Inventors: H. Eberhard Lange, Klaus Theurich
  • Patent number: 10409660
    Abstract: This storage system has a plurality of modules that encode data being written to a storage medium and decode data being read from said storage medium. The storage system also has an adapter that controls the reading and writing of data from and to the storage medium such that, when an error is detected and determined to be the error of at least one of said plurality of modules, the adapter prevents the module(s) in question from being used to read or write data.
    Type: Grant
    Filed: June 5, 2015
    Date of Patent: September 10, 2019
    Assignee: HITACHI LTD.
    Inventors: Mioko Moriguchi, Etsutaro Akagawa
  • Patent number: 10394671
    Abstract: The invention relates to a fault-tolerant, maintainable automation system comprising two central computers, a process periphery and gateway computers, wherein the central computers and the gateway computers are fail-silent FCUs and represent autonomous exchange units, and the central computers and gateway computers exchange timed status messages via communications channels, and wherein each gateway computer establishes the link to the process periphery associated with the gateway computer and saves the current status of the process periphery associated with the gateway computer, and wherein a central computer assumes the role of an active central computer and another central computer assumes the role of a passive central computer, and wherein the active central computer exerts control over the gateway computers, and wherein the active central computer transmits a sign-of-life message to the passive central computer, preferably periodically, and wherein the passive central computer acknowledges the receipt of
    Type: Grant
    Filed: July 17, 2015
    Date of Patent: August 27, 2019
    Assignee: TTTech Computertechnik AG
    Inventor: Hermann Kopetz
  • Patent number: 10394669
    Abstract: The invention relates to a method for periodic transmission of real time data in a computer system, particularly a distributed computer system, which computer system is comprised of node computers (201-208), particularly an appreciable number of node computers (201-208), and distributor units (211-215), particularly an appreciable number of distributor units (211-215), wherein the node computers (201-208) and the distributor units (211-215) have access to a global time, and wherein real time data are transmitted by means of time-triggered real time messages, wherein selected distributor units (212, 213, 214, 215) form a central structure of distributor units; and wherein during a periodic communication round (PCR), in the error-free case, at least two copies of each real time message to be sent are transmitted via at least two independent routes through the central structure, by executing a satisfying or an optimal time plan, from a start distributor unit in the central structure to a target distributor unit
    Type: Grant
    Filed: October 14, 2016
    Date of Patent: August 27, 2019
    Assignee: TTTech Computertechnik AG
    Inventor: Stefan Poledna
  • Patent number: 10386913
    Abstract: In one embodiment, a system includes a number of networking modules. Each module includes a respective voltage controller and a voltage-configuration circuit. The voltage-configuration circuit includes a number of transistors that are each coupled to a respective resistor. The system also includes one or more processors coupled to the voltage controllers including instructions executable by the processors. The processors being operable when executing the instructions to configure, for each module, an on-state or off-state of the transistors coupled to the respective resistor. The transistors coupled to the respective resistor correspond to a bit of a number of under-voltage thresholds. The processors are also operable to preset, during a module initialization, a relative ranking of under-voltage shutdown between the modules by setting the transistors. At least one of the number of networking modules has a different under-voltage threshold level relative to another one of the networking modules.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: August 20, 2019
    Assignee: Platina Systems Corporation
    Inventors: Frank Szu-Jen Yang, Jason Luo Pang
  • Patent number: 10379971
    Abstract: Techniques are provided for overcoming failures in a memory. One portion of the memory may operate in a single chip spare mode. Upon detection of an error in a single chip in the portion of the memory, a region of the portion of the memory may be converted to operate in a double chip spare mode. The memory may be accessed in both single and double chip spare modes.
    Type: Grant
    Filed: May 19, 2017
    Date of Patent: August 13, 2019
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Gary Gostin, Erin A. Handgen
  • Patent number: 10372520
    Abstract: Disclosed are systems, methods and non-transitory computer-readable mediums for dynamically presenting and updating a directed time graph displayed in a graphical user interface. In some examples, the method can include displaying a suggested path within a graphical user interface on a computer screen, the suggested path can include outstanding issues of elements of a network. The displaying the suggested path can include determining based on one or more factors an efficient ordering of the outstanding issues and ordering the outstanding issues based on the one or more factors. The method can also include monitoring, at regular intervals, updates to the one or more outstanding issues and automatically updating the suggested path, by a processor, based on the updates to the one or more outstanding issues.
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: August 6, 2019
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Jay Kemper Johnston, Magnus Mortensen, David C. White, Jr., Joseph Michael Clarke
  • Patent number: 10360133
    Abstract: Disclosed embodiments include a computer system for verifying proper configuration of analytic elements. The computer system identifies an analytic element associated with a network-connected software application. The computer system also executes the analytic element such that the analytic element initiates a network communication with a remote server. The computer system then searches a dataset for information relating to the network communication from the analytic element. The dataset comprises network communications received by a remote server. When the network communication generated by the analytic element is not found within the dataset, the computer system generates a report that the analytic element is not functioning properly.
    Type: Grant
    Filed: February 3, 2017
    Date of Patent: July 23, 2019
    Assignee: ObservePoint Inc.
    Inventors: John Raymond Pestana, Robert K. Seolas, Tyler Broadbent, Dan Reno, Gregory Larson
  • Patent number: 10353769
    Abstract: A storage system includes an interface and storage circuitry. The interface is configured to communicate with a plurality of memory cells coupled to multiple Bit Lines (BLs). The memory cells are programmed and read in sub-groups of multiple BLs, and the sub-groups correspond to respective addresses. The storage circuitry is configured to generate a sequence of addresses for reading memory cells that together store a data part and a pattern part containing a predefined pattern, via multiple respective sub-groups, to detect that the data part read from the memory cells is erroneous due to a fault that occurred in the sequence of addresses by identifying a mismatch between the pattern part read from the memory cells and the predefined pattern, and, in response to detecting the fault, to take a corrective measure to recover an error-free version of the data part.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: July 16, 2019
    Assignee: Apple Inc.
    Inventors: Charan Srinivasan, Eyal Gurgi
  • Patent number: 10346234
    Abstract: An apparatus including a physical memory partitioned into areas, a flag storage unit to store flags wherein a flag is set as indicating an area being updated when storage information stored in the area is updated, the area being associated with the flag, and a processor. The processor executes a first process of recording, when any fault does not occur, storage information stored in a first area to a recording device, the first area being associated with a first flag indicating the first area being updated, a process of saving, in a saving device, the storage information stored in the first area, and clearing the first flag so as to indicate the first area not being updated, and a second process of recording, to the recording device, storage information stored in a second area associated with a second flag indicating being updated when the fault occurs.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: July 9, 2019
    Assignee: FUJITSU LIMITED
    Inventor: Motoyoshi Hirose
  • Patent number: 10338984
    Abstract: Detecting a defective cell in a memory in consideration of an error property difference depending on the storage state. A determination unit determines whether there is a possibility of defect for each of unit-of-storages on a memory cell formed with a non-volatile memory. The non-volatile memory undergoes either a reset operation that transitions a state from a low resistive state (LRS) to a high resistive state (HRS) or a set operation that transitions the state from the high resistive state to the low resistive state. The determination unit determines a unit-of-storage in which the number of errors in predetermined one of the reset operation and the set operation has exceeded a predetermined standard, as a unit-of-storage suspected of having a defect.
    Type: Grant
    Filed: July 9, 2015
    Date of Patent: July 2, 2019
    Assignee: SONY CORPORATION
    Inventors: Yasushi Fujinami, Kenichi Nakanishi, Tsunenori Shiimoto, Tetsuya Yamamoto, Tatsuo Shinbashi, Hideaki Okubo, Haruhiko Terada, Ken Ishii, Hiroyuki Iwaki, Matatoshi Honjo
  • Patent number: 10339008
    Abstract: In some examples, a computing device may include a physical processor that executes machine readable instructions that cause the computing device to obtain, from the system, an actual value of a backup parameter for each backup parameter of a set of backup parameters. Each backup parameter may have a predefined threshold for the backup parameter. Execution of the machine readable instructions may further cause the computing device to determine a weightage for the backup parameter based on the predefined threshold and the actual value. The weightage may indicate a degree of contribution of the backup parameter for determining the type of backup to be executed in the system, and execution of the machine readable instructions may cause the computing device to determine the type of backup based on the weightage and the actual value of each backup parameter of the set of backup parameters.
    Type: Grant
    Filed: September 7, 2016
    Date of Patent: July 2, 2019
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Lokesh Murthy Venkatesh, Nandan Shantharaj, Sunil Turakani