Abstract: A speech coding system is provided where input speech is coded by finding via an evaluation computation a code vector giving a minimum error between reproduced signals obtained by linear prediction analysis filter processing, simulating speech path characteristics, on code vectors successively read out from a noise codebook storing a plurality of noise trains as code vectors and an input speech signal and by using a code specifying the code vector. In the speech coding system, the noise codebook includes a delta vector codebook which stores an initial vector and a plurality of delta vectors having difference vectors between adjoining code vectors. In addition, provision is made in the computing unit for the evaluation computation of a cyclic adding unit for cumulatively adding the delta vectors to virtually reproduce the code vectors.

Abstract: An interface device is provided for coupling a host device having a network interface to a computer network having a predetermined communications medium and a predetermined communications physical layer. The interface device comprises a plug member having a first connector affixed to it for coupling to the network interface of the host device. The interface device further includes front end circuitry disposed within the plug member, the front end circuitry being selectable to couple to the predetermined communications medium and to interact with the predetermined physical layer.

Abstract: A voice synthesizing apparatus is arranged to synthesize a voice from text data composed of either character codes or a series of symbols by generating a sound source based on a series of sound-source parameters and synthesizing the sound source on the basis of a series of synthesis parameters. The voice synthesizing apparatus is provided with a sound-source generating circuit for generating the aforesaid sound source from a signal obtained from an instrumental sound generated with a musical instrument. This arrangement serves to easily synthesize voices which convey language information and yet which simulate the sounds of musical instruments such as a guitar, a violin, a harmonica, a musical synthesizer and the like.

Abstract: This invention has an object to provide a practical neural network device. The first neural network device of this invention comprises an input circuit for performing predetermined processing of external input information and generating an input signal, an arithmetic processing circuit for performing an arithmetic operation of the input signal in accordance with a plurality of control parameters and generating an output signal, and a control circuit for controlling the control parameters of the arithmetic processing circuit so that the output signal is set to satisfy a predetermined relationship with the input signal, the control circuit including a first cumulative adder for performing cumulative summation of updating amounts of the control parameters for a plurality of proposition patterns supplied as the input signal during learning, and a second cumulative adder for adding currently used control parameter values to values obtained by the first cumulative adder to obtain new control parameter values.

Abstract: A network structure for path generation includes an operational amplifier circuit (200) implementation. The circuit (200) implements a finite difference approximation template for computing the weighted sum of its four "neighbors." The circuit implementation (200) includes a series of five output operational amplifiers (202, 204, 206, 208 and 210). Each of the output amplifiers includes a feedback path (212) having a feedback resistance, and is connected to the output terminal of its respective operational amplifier and to the negative input terminal (214) of the corresponding amplifier. The positive input terminal (216) of each of the output operational amplifiers is connected to a ground (218). The circuit implementation (200) further includes a series of input operational amplifiers (220, 222, 224, 226 and 228). The output terminals (230) of each of the input operational amplifiers are connected to respective ones of the input terminals (214) of the output operational amplifiers through input impedances.

Abstract: In a method of retrieving optimum case information for a current problem, case candidates having features of the current problem and common features are retrieved from information representing a plurality of cases stored in a case base in response to presentation of the current problem. A storing unit stores the case base, and respective cases include case problems and solutions or solving methods for the case problems. An optimum case candidate among case candidates is determined from a group of features of the current problem, a group of common features and a group of features of problems of respective case candidates in accordance with influence relation information indicating a feature group influenced by other feature groups. Case information corresponding to the optimum case candidate is retrieved from information representing a plurality of cases.

Abstract: An apparatus for storing and retrieving data is described. The apparatus includes a circuitry for initiating data transmission, a first memory, a second memory, and a multiline bus for transferring control information, addresses, and the data. The control information includes information for selecting one of the first and second memories without using any separate memory select line. Configuration circuitry is provided for assigning a first identification value to the first memory and a second identification value to the second memory.

Abstract: An expert system building method wherein, in an expert system which executes an inference process according to a decision tree, at least one data unit or any combination of such data units of data forming an input/output information is made. Next, a data input/output method is specified on the basis of relationship between the at least one data unit and the input/output information. Thus, data possibly needed can be stored simultaneously. The expert system can execute an inference process according to the decision tree having the expert's knowledge described as they are with no relation to the data input, and the data can be simultaneously entered in units which are easy to understand by an end user with no relation to the process of the decision tree.

Abstract: A user-programmable FPGA architecture includes a plurality of logic function circuits including inputs and outputs disposed on an integrated circuit. A plurality of input/output (I/O) modules are also disposed on the integrated circuit and each include an input buffer having an input connected to I/O pad on the integrated circuit and an output connected to an output node, and an output buffer having an input connected to an input node, an output connected to the I/O pad, and a control input connected to a control node. A general interconnect structure disposed on the integrated circuit includes a plurality of interconnect conductors which may be connected to one another, to the inputs and outputs of the logic function circuits, and to the I/O modules by programming user-programmable interconnect elements. Direct interconnections are made between the inputs of selected ones of the logic function circuits and the output nodes of selected ones of the I/O modules.

Abstract: A latch manager enabling multiple processors in a multiprocessor system to gain access to a shared resource. Resource access is controlled by the use of a latch-control word. There is one latch-control word associated with each of the shared resources in the system. The latch-control word can reside either in the shared resource itself or in a separate common area of the system to which each of the processors has access. The latch-control word is captured by the requesting processor and its contents are modified to indicate that the requesting processor owns the latch (either in a shared or exclusive state) or that it is making a request to own the latch at the first opportunity. If the processor was not able to gain ownership of the latch upon its initial capture, the denied processor will wait and monitor the latch until it has been promoted to ownership of the latch. Optionally, the processor can back out of the request and continue processing.

Abstract: A method and apparatus for allocating transmission bits for use in transmitting samples of a digital signal. An aggregate allowable quantization distortion value is selected representing an allowable quantization distortion error for a frame of samples of the digital signal. A set of samples are selected from the frame of samples such that a plurality of the selected samples are greater than a noise threshold. For each sample of the set, a sample quantization distortion value is computed which represents an allowable quantization distortion error for the sample. The sum of all sample quantization distortion values is approximately equal to the aggregate allowable quantization distortion value. For each sample of the set, a quantization step size is selected which yields a quantization distortion error approximately equal to the sample's corresponding quantization distortion value. Each sample is then quantized using its quantization step size.

Abstract: A fault-tolerant computer system employs a power supply system including a battery backup so that upon AC power failure the system can execute an orderly shutdown, saving state to disk. A restart procedure restores the state existing at the time of power failure if the AC power has been restored by the time the shutdown is completed. This powerfail/autorestart procedure may be implemented in a fault-tolerant multiprocessor configuration having multiple identical CPUs executing the same instruction stream, with multiple, identical memory modules in the address space of the CPUs storing duplicates of the same data. The system detects faults in the CPUs and memory modules, and places a faulty unit offline while continuing to operate using the good units.

Abstract: A knowledge-based system (10) which combines case-based reasoning, heuristic search and deductive rule application. The resulting inference engine is sensitive to the context of problem solving. The system (10) includes a heuristic searcher (22), a case memory (14), a rule memory (18), a rule applier (26) and a case matcher (24). The rule applier (26) uses stored rules to elaborate on new cases by deriving new features so that it will be closer to selected old cases. The case matcher (24) detects how close selected cases are to the new case and generates a score for the match. The heuristic searcher (22) maintains a plurality of elaborated cases and determines the goodness of each elaborated case, the goodness being a measure of the match between the elaborated case and the selected old case.

Abstract: A bus arbitration scheme for controlling access or mastership of a bus is disclosed. Priority of access to the bus is based not only on the time relationship of the requests for use of the bus arriving at the arbiter but also on the relative priority of each request. Thus a higher priority request will gain access to the bus before a lower priority one even if this latter request arrived at the arbiter first. The arbitration scheme is implemented by a series of logic gates.

Abstract: Signal processing structures for providing direct prediction coefficients and direct Least Square-Finite Impulse Response (LS-FIR) filter coefficients. The structures include one or more processors, and a storage and retrieval structure for selectively storing predictor and filter coefficients and intermediate variables, to thereby allow the one or more real processors to emulate a plurality of virtual processors, which take the form of a side fed superlattice structure, in the case of linear prediction, and a side-fed superlattice-superladder structure, in the case of direct LS-FIR filtering.

Abstract: A speech recognition system includes a parameter extracting section for extracting a speech parameter of input speech, a first recognizing section for performing recognition processing by word-based matching, and a second recognizing section for performing word recognition by matching in units of word constituent elements. The first word recognizing section segments the speech parameter in units of words to extract a word speech pattern and performs word recognition by matching the word speech pattern with a predetermined word reference pattern. The second word recognizing section performs recognition in units of word constituent elements by using the extracted speech parameter and performs word recognition on the basis of candidates of an obtained word constituent element series.

Abstract: A speech categorization system includes first and second timers which generate first and second measured durations indicative of duration of selected higher and lower amplitude segments included in a voice message. A higher amplitude segment is classified in a first category when the first and second measured durations corresponding to the higher amplitude segment and an adjacent lower amplitude segment satisfy a classification test, and a counter counts the number of the higher amplitude segments classified in the first category Accented syllables in the higher amplitude segment are recognized to aid classification.

Abstract: An arbitration mechanism for controlling a coupling order between a number of resources and a number of requesters having a number of requests processing units, one associated with each one of the requesters, for receiving a resource type request signal from the associated requester, a number of grant processing units, one associated with each one of the resources, for monitoring a busy status signal from said associated resource, a common broadcast medium coupled to the number of request processing units and the grant processing units, and an arbiter for granting access to said common broadcast medium to one of the request processing units and the grant processing units using the common broadcast medium to control the coupling order between the requesters and the resources in a first come, first served manner.

Abstract: An exemplary CELP coder where gain adaptation is performed using previous gain values in conjunction with an entry in a table comprising the logarithms of the root-mean-squared values of the codebook vectors, to predict the next gain value. Not only is this method less complex because the table entries are determined off-line, but in addition the use of a table at both the encoder and the decoder allows fixed-point/floating-point interoperability requirements to be met.

Abstract: A learning control method reduces overall learning time by displaying data related to an appropriate determination of learning protraction and a proper restoring method. Prior to initiating the learning, the user is inquired about the current problem and a problem data set representing items associated with the problem is obtained. Evaluation data indicating a state of learning obtained during the learning on the current problem is sequentially stored and displayed. When there is a high possibility of learning protraction during the learning, a message informing the user is displayed. When the learning is stopped by the user in this case, the problem data set and evaluation data set are stored. Then, a list of restoring methods is displayed and a particular restoring method is selected by the user once the learning is stopped. The learning is restarted on the current problem in accordance with the selected restoring method.