Patents Examined by Michael Shingleton
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Patent number: 10054810Abstract: A display apparatus includes at least one pixel structure, which includes an active device, an electric insulation layer and a pixel electrode. The electric insulation layer is disposed on the active device. The electric insulation layer has a trench and a via. The via is located on a bottom surface of the trench. A portion of the electric insulation layer surrounding the trench is monolithically connected to another portion of the electric insulation layer surrounding the via. A pixel electrode has a first electrode portion and a second electrode portion connected to each other. The first electrode portion is located in the trench. A thickness of the first electrode portion is less than a depth of the trench. The second electrode portion is located in the via and is electrically connected to the active device through the via.Type: GrantFiled: July 6, 2017Date of Patent: August 21, 2018Assignee: E Ink Holdings Inc.Inventors: Xue-Hung Tsai, Wei-Tsung Chen, Henry Wang, Po-Hsin Lin
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Patent number: 10050051Abstract: A memory device includes memory includes a multi-layers stack includes a plurality of insulating layers and a plurality conductive layers alternatively stacked on a semiconductor device, a plurality of memory cells formed on the conductive layers, a contact plug passing through the insulating layers and the conductive layers, and a dielectric layer including a plurality of extending parts each of which is inserted between each adjacent two ones of the insulating layers to isolate the conductive layer from the contact plug, wherein any one of the extending parts that has a shorter distance departed from the semiconductor substrate has a size substantially greater than a size of the others that has a longer distance departed from the semiconductor substrate.Type: GrantFiled: March 22, 2017Date of Patent: August 14, 2018Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Ting-Feng Liao, I-Ting Lin
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Patent number: 10050105Abstract: To provide an optimal structure for electrically connecting an MOSFET region, a FWD region, and an IGBT region in parallel within one semiconductor chip by mitigating electric field concentration between a SJ column and a drift region, a semiconductor device is provided, the semiconductor device including: a semiconductor substrate: a super junction MOSFET having a repetitive structure of a first column and a second column; a parallel device having a drift region including second conductivity-type impurities, and being provided separately from the super junction MOSFET in the semiconductor substrate; and a boundary portion located between the super junction MOSFET and the parallel device in the semiconductor substrate, wherein the boundary portion extends from one main surface side to the other main surface side, and has at least one third column having first conductivity-type impurities, and the third column is shallower than the first column and the second column.Type: GrantFiled: November 29, 2016Date of Patent: August 14, 2018Assignee: FUJI ELECTRIC CO., LTD.Inventors: Tohru Shirakawa, Tatsuya Naito, Isamu Sugai
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Patent number: 10049963Abstract: A power electronics module is provided having one or more power converter semiconductor components. The power electronics module further has a substrate having a first surface to which the one or more components are mounted, and having an opposing second surface from which project a plurality of heat transfer formations for enhancing heat transfer from the substrate. The power electronics module further has a coolant housing which sealingly connects to the substrate to form a void over the heat transfer formations of the second surface. The coolant housing has an inlet for directing a flow of an electrically insulating coolant into the void and an outlet for removing the coolant flow from the void, whereby heat generated during operation of the one or more components is transferred into the coolant flow via the substrate.Type: GrantFiled: March 21, 2017Date of Patent: August 14, 2018Assignee: ROLLS-ROYCE plcInventors: Kalyani G Menon, Richard Harwood
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Patent number: 10043810Abstract: A dynamic random access memory (DRAM) is provided. The DRAM comprises a substrate, a plurality of isolation structures, a plurality of word lines, a plurality of bit line contacts and a plurality of buried bit lines. The isolation structures are located in the substrate and defines a plurality of active regions extending along a first direction. The word lines are located in the substrate and are extending along a second direction, the second direction intersects with the first direction. The bit line contacts are located above the isolation structures, wherein each of the bit line contacts have a diffusion region that defines a bit line side contact. The buried bit lines are located above the bit line contacts and are connected to the active region via the bit line side contact, the buried bit lines are extending along the first direction and is parallel with the plurality of active regions.Type: GrantFiled: August 18, 2017Date of Patent: August 7, 2018Assignee: Winbond Electronics Corp.Inventor: Noriaki Ikeda
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Patent number: 10032892Abstract: This semiconductor device comprises an active layer that is formed of an oxide magnetic material and a porous dielectric body that contains water and is provided on the active layer. By using hydrogen ions and hydroxide ions which are formed by electrolysis of water, the crystal structure of the active layer is changed between a ferromagnetic metal and an antiferromagnetic insulating body.Type: GrantFiled: January 6, 2016Date of Patent: July 24, 2018Assignee: National University Corporation Hokkaido UniversityInventors: Hiromichi Ohta, Takayoshi Katase, Yuki Suzuki
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Patent number: 10032937Abstract: A semiconductor device structure includes a region of semiconductor material with a first major surface and an opposing second major surface. A contact structure is disposed in a first portion of the region of semiconductor material and includes a tub structure extending from adjacent a first portion of the first major surface. A plurality of structures comprising portions of the region of semiconductor material extend outward from a lower surface of the tub structure. In some embodiments, the plurality of structures comprises a plurality of free-standing structures. A conductive material is disposed within the tub structure and laterally surrounding the plurality of structures. In one embodiment, the contact structure facilitates the fabrication of a monolithic series switching diode structure having a low-resistance substrate contact.Type: GrantFiled: November 11, 2016Date of Patent: July 24, 2018Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Ali Salih, Gordon M. Grivna, Daniel R. Heuttl, Osamu Ishimaru, Thomas Keena, Masafumi Uehara
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Patent number: 10006822Abstract: A semiconductor sensor assembly for use in a corrosive environment comprises a processing device comprising at least one first bondpad of a material which may be corroded by a corrosive component in a corrosive environment; a sensor device comprising at least one second bondpad consisting of and/or being covered by a first corrosion resistant material; at least one bonding wire for making a signal connection between the at least one first bondpad of the processing device and the second bondpad of the sensor device. The processing device is partially overmoulded by a second corrosion resistant material, and is partially exposed to a cavity in the corrosion resistant material, with the sensor device being present in the cavity. A redistribution layer is provided to enable signal connection between the processing device and the sensor device is physically made in the cavity while the second corrosion resistant material covers the first bondpad.Type: GrantFiled: June 21, 2017Date of Patent: June 26, 2018Assignee: MELEXIS TECHNOLOGIES NVInventors: Jian Chen, Laurent Otte
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Patent number: 10008441Abstract: A semiconductor package includes a circuit board, a semiconductor chip, a heat spreading layer, an encapsulant layer, a plurality of conductive connections, and a plurality of solder balls. The circuit board includes opposite first and second surfaces and a plurality of through holes. The semiconductor chip is formed over a center portion of the first surface of the circuit board, having an active surface facing the circuit board. The heat spreading layer is formed over the semiconductor chip. The encapsulant layer is formed over the circuit board, covering heat spreading layer, the semiconductor chip, and the circuit board. The plurality of conductive connections respectively passes through the through holes and electrically connecting the semiconductor chip with the circuit board. The plurality of solder balls are formed over the second surface of the circuit board.Type: GrantFiled: November 11, 2016Date of Patent: June 26, 2018Assignee: MEDIATEK INC.Inventor: Shiann-Tsong Tsai
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Patent number: 10008616Abstract: The electronic device having a Schottky diode includes first and second electrodes disposed on a semiconductor substrate and spaced apart from each other. A first semiconductor region is formed within the semiconductor substrate. The first semiconductor region may include a first surface portion in contact with the second electrode, forming a Schottky diode with the second electrode. A second semiconductor region having the same conductivity-type as the first semiconductor region and overlapping the first electrode is formed within the semiconductor substrate. A third semiconductor region having a different conductivity-type from the first semiconductor region, and having a first portion and a second portion spaced apart from each other, is formed within the semiconductor substrate. An isolation region is disposed between the second and the third semiconductor regions. The isolation region includes a first isolation portion and a second isolation portion spaced apart from each other.Type: GrantFiled: March 22, 2017Date of Patent: June 26, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yong Don Kim, Seo In Pak
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Patent number: 10002875Abstract: A semiconductor device may include gate electrodes and interlayer insulating layers alternately stacked on a substrate, a channel layer penetrating the gate electrodes and the interlayer insulating layers, a gate dielectric layer between the gate electrodes and the channel layer, a filling insulation that fills at least a portion of an interior of the channel layer, a charge fixing layer between the channel layer and the filling insulation and including a high-k material and/or a metal, and a conductive pad connected to the channel layer and on the filling insulation. The conductive pad may be physically separated from the charge fixing layer.Type: GrantFiled: March 22, 2017Date of Patent: June 19, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Phil Ouk Nam, Hyung Joon Kim, Sung Gil Kim, Ji Hoon Choi, Seulye Kim, Hong Suk Kim, Jae Young Ahn
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Patent number: 10002837Abstract: A semiconductor device includes a metal member, a first semiconductor chip, a second semiconductor chip, a first solder and a second solder. A quantity of heat generated in the first semiconductor chip is greater than the second semiconductor chip. The second semiconductor chip is formed of a material having larger Young's modulus than the first semiconductor chip. The first semiconductor chip has a first metal layer connected to the metal member through a first solder at a surface facing the metal member. The second semiconductor chip has a second metal layer connected to the metal member through a second solder at a surface facing the metal member. A thickness of the second solder is greater than a maximum thickness of the first solder at least at a portion of the second solder corresponding to a part of an outer peripheral edge of the second metal layer.Type: GrantFiled: April 15, 2016Date of Patent: June 19, 2018Assignee: DENSO CORPORATIONInventors: Kenji Onoda, Syoichirou Oomae
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Patent number: 9997413Abstract: A semiconductor structure containing a plurality of stacked vertical field effect transistor (FETs) is provided. After forming a first vertical FET of a first conductivity type at a lower portion of a semiconductor fin, a second vertical FET of a second conductivity type is formed on top of the first vertical FET. The second conductivity type can be opposite to, or the same as, the first conductivity type. A source/drain region of the first vertical FET is electrically connected to a source/drain region of the second vertical FET by a conductive strip structure.Type: GrantFiled: March 22, 2017Date of Patent: June 12, 2018Assignee: International Business Machines CorporationInventor: Effendi Leobandung
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Patent number: 9997427Abstract: A display panel includes a first inorganic capping layer (INOCL) in a non-displaying area (AND) of a substrate, a first electrode in the AND formed on the first INOCL, an organic capping layer (OCL) on the substrate overlapping at least a portion of the first electrode, and a first dam structure in the AND positioned between a first lateral surface of the substrate and the OCL in top view. A first distance H is between the top surfaces of the first INOCL and the OCL in a normal direction of the substrate. The first dam structure has a first maximum dam height Hdam and a dam width Wdam. A second distance Lsr is a minimum distance from a third lateral surface of the first dam structure to a second lateral surface of the first electrode, wherein H, Lsr, Hdam and Wdam conform to the equation: H×(0.1870?Wdam/(2.46×Lsr))?Hdam?H×(0.9548?Wdam/(44.26×Lsr)).Type: GrantFiled: August 18, 2017Date of Patent: June 12, 2018Inventors: Yang-Chen Chen, Nai-Fang Hsu, Yu-Hsien Wu
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Patent number: 9998087Abstract: An integrated structure of power amplifier and acoustic wave device comprises: a compound semiconductor epitaxial substrate including an epitaxial structure formed on a compound semiconductor substrate, a power amplifier upper structure formed on a top-side of a left part of the compound semiconductor epitaxial substrate, and a film bulk acoustic resonator formed on the top-side of a right part of the compound semiconductor epitaxial substrate; wherein the left part of the compound semiconductor epitaxial substrate and the power amplifier upper structure form a power amplifier; the right part of the compound semiconductor epitaxial substrate and the film bulk acoustic resonator form an acoustic wave device; the integrated structure of power amplifier and acoustic wave device on the same compound semiconductor epitaxial substrate is capable of reducing the component size, optimizing the impedance matching, and reducing the signal loss between power amplifier and acoustic wave device.Type: GrantFiled: January 25, 2017Date of Patent: June 12, 2018Assignee: WIN SEMICONDUCTORS CORP.Inventors: Shu-Hsiao Tsai, Re Ching Lin, Pei-Chun Liao, Cheng-Kuo Lin, Yung-Chung Chin
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Patent number: 9997629Abstract: An integrated circuit device includes a fin having a gate area beneath a gate electrode structure, a source/drain region disposed beyond ends of the fin, and a first conformal layer formed around an embedded portion of the source/drain region. A vertical sidewall of the first conformal layer is oriented parallel to the gate area.Type: GrantFiled: June 13, 2016Date of Patent: June 12, 2018Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Hou-Ju Li, Kao-Ting Lai, Kuo-Chiang Ting, Chi-Hsi Wu
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Patent number: 9997681Abstract: One embodiment relates to a lens comprising: a lower end portion having an incident surface to which light is incident; and an upper end portion having an emitting surface allowing the light having passed through the incident surface to pass therethrough, wherein the ratio of an incidence angle and an emission angle on a first plane and/or the ratio of an incidence angle and an emission angle on a second plane is smaller than the ratio of an incidence angle and an emission angle on a third plane, the incidence angle is an angle of the light incident to the incident surface with respect to a center axis, the emission angle is an angle of the light emitted from the emitting surface with respect to the center axis, each of the first to third planes is a plane passing the center axis and is parallel to a first direction, the first plane is perpendicular to the second plane, the third plane is positioned between the first plane and the second plane, the center axis passes the center of the lens and is parallel toType: GrantFiled: January 15, 2016Date of Patent: June 12, 2018Assignee: LG INNOTEK CO., LTD.Inventor: Ki Hyun Kim
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Patent number: 9997513Abstract: A multi-chip device can include stacked semiconductor devices including a top and bottom semiconductor device. The top semiconductor device can include a first circuit. The bottom semiconductor device can include a first through via and a first ESD protection circuit electrically connected to an external electrical connection of the device. The first ESD protection circuit can include a first ESD protection structure. The first through via can provide an electrical connection through the bottom semiconductor device between the external electrical connection and a first terminal of the first circuit, which can be free of an electrical connection to an ESD protection circuit having the first ESD protection structure.Type: GrantFiled: July 10, 2017Date of Patent: June 12, 2018Inventor: Darryl G. Walker
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Patent number: 9979353Abstract: Aspects of the present disclosure are generally directed to a power supply for generating an output supply voltage. The power supply generally includes a variable voltage supply configured to generate an intermediate supply voltage based on a reference signal, a correction circuit configured to generate an error signal based on the output supply voltage or the intermediate supply voltage, and a combiner configured to combine the intermediate supply voltage and the error signal to provide the output supply voltage.Type: GrantFiled: March 23, 2017Date of Patent: May 22, 2018Assignee: SnapTrack, Inc.Inventors: Martin Paul Wilson, Shane Flint
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Patent number: 9978781Abstract: A display device including: a substrate including a display area for displaying an image and a non-display area positioned at a periphery of the display area; a plurality of pixels positioned at the display area; a plurality of data lines connected with the plurality of pixels; and a crack detecting line positioned at the non-display area, wherein the crack detecting line includes: a plurality of unit connectors extending in a first direction, wherein the first direction is parallel to an extending direction of a side of the substrate nearest to the unit connectors; and a plurality of wiring portion units connected to each other through the plurality of unit connectors, wherein the number of wiring portion units is an even number.Type: GrantFiled: March 22, 2017Date of Patent: May 22, 2018Assignee: SAMSUNG DISPLAY CO., LTD.Inventors: Hey Jin Shin, Won Kyu Kwak, Seung-Kyu Lee