Abstract: Disclosed is a semiconductor device including two oxide semiconductor layers, where one of the oxide semiconductor layers has an n-doped region while the other of the oxide semiconductor layers is substantially i-type. The semiconductor device includes the two oxide semiconductor layers sandwiched between a pair of oxide layers which have a common element included in any of the two oxide semiconductor layers. A double-well structure is formed in a region including the two oxide semiconductor layers and the pair of oxide layers, leading to the formation of a channel formation region in the n-doped region. This structure allows the channel formation region to be surrounded by an i-type oxide semiconductor, which contributes to the production of a semiconductor device that is capable of feeding enormous current.

Abstract: An integrated circuit device includes a fin having a gate area beneath a gate electrode structure, a source/drain region disposed beyond ends of the fin, and a first conformal layer formed around an embedded portion of the source/drain region. A vertical sidewall of the first conformal layer is oriented parallel to the gate area.

Abstract: A photoelectric conversion device includes a semiconductor substrate, an insulating layer provided on the semiconductor substrate, an electrode provided on the insulating layer, a photoelectric conversion film provided on the electrode for converting received light to charges, a line connected between the electrode and the semiconductor substrate, a first planar electrode provided in the insulating layer and connected to the electrode, and a second planar electrode provided in the insulating layer between the first planar electrode and the semiconductor substrate.

Abstract: A sensor device and a manufacturing method thereof are provided in which no resin seal is used when a sensor is packaged, a change in connection relation according to a change in specifications of the control IC and others is facilitated when a control IC is packaged together with the sensor and high reliability is kept. The sensor device of the present invention includes a substrate containing an organic material and being formed a wiring, a sensor arranged on the substrate and electrically connected to the wiring, and a package cap arranged on the substrate and containing an organic material and covering the sensor, and the inside of the package cap is hollow.

Abstract: A phosphor has the general formula (M2x,M3y,M4z)mM1O3X(2/n), wherein M1 represents at least one element including at least Si and selected from the group consisting of Si, Ge, Ti, Zr, and Sn, M2 represents at least one element including at least Ca and selected from the group consisting of Ca, Mg, Cd, Co, and Zn, M3 represents at least one element including at least Sr and selected from the group consisting of Sr, Ra, Ba, and Pb, X represents at least one halogen element, M4 represents at least one element including at least Eu2+ and selected from the group consisting of rare-earth elements and Mn, m is in the range 1?m?4/3, n is in the range 5?n?7, and x, y, and z are each in such a range as to satisfy x+y+z=1, 0.45?x?0.8, 0.05?y?0.45, and 0.45, and 0.03?z?0.35.

Abstract: An area sensor of the present invention has a function of displaying an image in a sensor portion by using light-emitting elements and a reading function using photoelectric conversion devices. Therefore, an image read in the sensor portion can be displayed thereon without separately providing an electronic display on the area sensor. Furthermore, a photoelectric conversion layer of a photodiode according to the present invention is made of an amorphous silicon film and an N-type semiconductor layer and a P-type semiconductor layer are made of a polycrystalline silicon film. The amorphous silicon film is formed to be thicker than the polycrystalline silicon film. As a result, the photodiode according to the present invention can receive more light.

Abstract: A PN junction includes first and second areas of silicon, wherein one of the first and second areas is n-type silicon and the other of the first and second areas is p-type silicon. The first area has one or more projections which at least partially overlap with the second area, so as to form at least one cross-over point, the cross-over point being a point at which an edge of the first area crosses over an edge of the second area.

Abstract: A bipolar transistor includes a substrate of semiconductor material, a high-mobility layer in the substrate, and a donor layer adjacent to the high-mobility layer. An emitter terminal forms an emitter contact on the donor layer, and a collector terminal forms a collector contact on the donor layer. A base terminal is electrically conductively connected with the high-mobility layer. The transistor can be produced in a HEMT technology or BiFET technology in GaAs.

Abstract: An Electro-Static-Discharge (ESD) protection circuit uses Silicon-On-Insulator (SOI) transistors with buried oxide but no parasitic substrate diode useable for ESD protection. A filter voltage is generated by a resistor and capacitor. When a VDD-to-VSS ESD positive pulse occurs, the filter voltage passes through an n-channel pass transistor and inverted to drive a gate of a big SOI transistor that shunts ESD current. A second path is used for a VSS-to-VDD ESD positive pulse. The filter voltage passes through a p-channel pass transistor to the gate when the positive ESD pulse is applied to VSS. The big SOI transistor can connect between VDD and VSS for a power clamp, and the gates of the n-channel and p-channel pass transistors connect to VDD. A small diode may be added between VDD and VSS to generate a small triggering current to activate grounded-gate transistors near I/O pads for full-chip Pad-based ESD protection.

Abstract: The width of a heavily-doped sinker is substantially reduced by forming the heavily-doped sinker to lie in between a number of closely-spaced trench isolation structures, which have been formed in a semiconductor material. During drive-in, the closely-spaced trench isolation structures significantly limit the lateral diffusion.

Abstract: A tensile strain state in semiconductor components is adjusted. A pretensioned (tensile strain) layer is applied to a substrate (FIG. 1, (A)). Bridge structures (FIG. 1, (B)) are introduced in the layers by lithography and etching. The bridges are connected to the layer on both sides and are thus continuous. The geometric shape of the bridges, formed with a cross-section modulation, is determined by the windows (FIG. 1 (C)) in the layer. When the substrate is etched selectively, the bridge is undercut through the windows. The geometric structuring of the cross-section (FIG. 1, (D)) causes a redistribution of the originally homogeneous strain when the bridges are detached from the substrate, with the larger cross-sections relaxing at the expense of the smaller cross-sections, where the pretension is increased. Only a multiplication of stresses (or strain) originally present in the sample is possible, with the multiplication factor determined by lengths, widths and depths, and/or the relationships thereof.

Abstract: A vertical-mode tunnel field-effect transistor (TFET) is provided with an oxide region that may be laterally positioned relative to a source region. The oxide region operates to reduce a tunneling effect in a tunnel region underlying a drain region, during an OFF-state of the TFET. The reduction in tunneling effect results in a reduction or elimination of a flow of OFF-state leakage current between the source region and the drain region. The TFET may have components made from group III-V compound materials.

Abstract: A metal-insulator-metal (MIM) capacitor reduces a number of masks and processing steps compared to conventional techniques. A first conductive layer of a MIM capacitor is deposited on a semiconductor chip and patterned using a MIM conductive layer mask. A conductive redistribution layer (RDL) is patterned over the MIM dielectric layer. The conductive redistribution layer includes two RDL nodes that overlap the first conductive layer of the MIM capacitor. A conductive via or bump extends through the MIM dielectric layer and couples one of the RDL nodes to the first conductive layer of the MIM capacitor.

Abstract: The present disclosure provides a gas sensor including: a substrate; an electrode formed on the substrate; and a gas-sensing layer formed on the electrode, wherein the gas-sensing layer is a self-heating nanocolumnar structure having nanocolumns formed on the electrode and inclined with respect to the electrode with an angle of 60-89° and gas diffusion pores formed between the nanocolumns. The gas sensor according to the present disclosure requires no additional heater since it self-heats owing to the nanocolumnar structure and exhibits superior gas sensitivity even when no heat is applied from outside. Also, it can be mounted on mobile devices such as mobile phones because it consumes less power.

Abstract: An organic light-emitting display apparatus may include a substrate; a thin-film transistor (TFT) disposed on the substrate, and having an active layer, a gate electrode, a source electrode and a drain electrode; a signal line formed on the same layer as the source electrode and the drain electrode; a first insulating layer covers the signal line, the source electrode, and the drain electrode; a pixel electrode formed on the first insulating layer, and electrically connected to the TFT; a pixel-defining layer formed on the first insulating layer, includes an opening exposing the pixel electrode; an intermediate layer formed on the pixel electrode, and includes a light-emitting layer; and an opposite electrode formed on the intermediate layer. The intermediate layer is formed on the pixel-defining layer so as to overlap with the signal line.

Abstract: To provide a resistance change element which does not require a forming process and enables reduction of power consumption and miniaturization of the element, and to provide a method for producing it. A resistance change element 1 according to an embodiment of the present invention includes a bottom electrode layer 3, a top electrode layer 5 and an oxide semiconductor layer 4. The oxide semiconductor layer 4 has a first metal oxide layer 41 and a second metal oxide layer 42. The first metal oxide layer 41 is formed between the bottom electrode layer 3 and the top electrode layer 5, and in ohmic contact with the bottom electrode layer 3. The second metal oxide layer 42 is formed between the first metal oxide layer 41 and the top electrode layer 5, and in ohmic contact with the top electrode layer 5.

Abstract: An optoelectronic semiconductor device including a carrier substrate and at least one semiconductor chip arranged thereon, wherein the semiconductor chip includes an active layer that generates radiation, conductor tracks electrically contacting the semiconductor chip arranged on the carrier substrate, the semiconductor chip is enclosed in a potting material, and the potting material includes at least a first potting layer, a second potting layer and a third potting layer, which differ from one another in at least one of: their material composition, their optical properties and their chemical properties.

Abstract: A semiconductor device includes a substrate; an inter layer dielectric disposed on the substrate; a TSV penetrating the substrate and the ILD. In addition, a plurality of shallow trench isolations (STI) is disposed in the substrate, and a shield ring is disposed in the ILD surrounding the TSV on the STI. During the process of forming the TSV, the contact ring can protect adjacent components from metal contamination.

Abstract: An electronic device (1) includes a semiconductor substrate (3) having a front surface (7), a first electrode (8) and a second electrode (9) disposed on the front surface (7) of the substrate (3), wherein the first electrode (8) and the second electrode (9) each have at least one epitaxial graphene monolayer (10). The at least one epitaxial graphene monolayer (10) of the first electrode (8) forms an ohmic contact with the substrate (3) and the at least one epitaxial graphene monolayer (10) of the second electrode (9) forms a Schottky barrier with the substrate (3).

Abstract: A semiconductor device is inhibited from being degraded in reliability. The semiconductor device has a tab including a top surface, a bottom surface, and a plurality of side surfaces. Each of the side surfaces of the tab has a first portion continued to the bottom surface of the tab, a second portion located outwardly of the first portion and continued to the top surface of the tab, and a third portion located outwardly of the second portion and continued to the top surface of the tab to face the same direction as each of the first and second portions. In planar view, the outer edge of the semiconductor chip is located between the third portion and the second portion of the tab, and the outer edge of an adhesive material fixing the semiconductor chip to the tab is located between the semiconductor chip and the second portion.