Patents Examined by Michael Sun
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Patent number: 10691486Abstract: A processor including computation groups, each computation group including computation cores, the processor being capable of simultaneously implementing a plurality of applications, each application being implemented by a computation core and possibly requiring a read-mode or write-mode access to an external memory connected to the processor. At least one core, called dedicated core, of at least one computation group is dedicated to management of the external memory, the management making it possible to temporally and spatially organize read-mode and write-mode accesses to the external memory of each application requiring a read or a write in the external memory implemented by the processor.Type: GrantFiled: September 25, 2017Date of Patent: June 23, 2020Assignee: Airbus Operations (S.A.S.)Inventors: Adrien Gauffriau, Benoît Triquet
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Patent number: 10678725Abstract: A semiconductor apparatus may include an interface circuit. The interface circuit may sense level variations of a first signal and a second signal. The interface circuit may generate first and second output signals by variably delaying the first and second signals depending on a sensing result. The interface circuit may transmit the first and second output signals to first and second signal transmission lines which are adjacent to each other.Type: GrantFiled: September 29, 2016Date of Patent: June 9, 2020Assignee: SK hynix Inc.Inventors: Jong Joo Shim, Hyung Soo Kim
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Patent number: 10681097Abstract: Methods and systems for transmitting data are presented. Data received from at least one data source is retained in at least one buffer. In one example, initial hierarchical data may be provided from the at least one buffer to a device, followed by additional hierarchical data. In one example, the data is received into the at least one buffer via a multicast connection, and the data is provided to the device via a point-to-point connection.Type: GrantFiled: July 13, 2017Date of Patent: June 9, 2020Assignee: OPENTV, INC.Inventor: John Tinsman
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Patent number: 10678728Abstract: A system on chip, semiconductor device, and/or method are provided that include a plurality of masters, an interface, and a semaphore unit. The interface interfaces the plurality of masters with a slave device. The semaphore unit detects requests of the plurality of masters, controlling the salve device, about an access to the interface and assigns a semaphore about each of the plurality of masters by a specific operation unit according to the detection result.Type: GrantFiled: November 15, 2018Date of Patent: June 9, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: DongSik Cho, Jeonghoon Kim, Rohitaswa Bhattacharya, Jaeshin Lee, Honggi Jeong
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Patent number: 10671395Abstract: The invention provides an application specific instruction set processor (ASIP) that uses a Very Long Instruction Word (VLIW) for simultaneously executing a plurality of operations. For simultaneously executing the plurality of operations, the ASIP processor comprises a fetching unit to fetch a long instruction word from an instruction memory unit and an instruction decoder unit that interfaces with the fetching unit and a program address counter. The instruction decoder unit decodes the long instruction word fetched from the instruction memory unit and enables a plurality of sub blocks responsible for execution of a plurality of simultaneous independent operations. The instruction decoder unit of the ASIP is capable of decoding a 32-bit instruction word and executing up to six simultaneous independent operations.Type: GrantFiled: February 13, 2017Date of Patent: June 2, 2020Assignee: The King Abdulaziz City for Science and Technology—KACSTInventors: Mohammed S BenSaleh, Abdulfattah M Obeid, Yousef A Alzahrani, Ahmed F Shalash, Hossam A Fahmy, Hossam A Sayed, Mohamed A Aly
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Patent number: 10671550Abstract: A computer-implemented method for offloading a problem having 2n size from processing circuitry to one or more accelerators is disclosed. The processing circuitry and the one or more accelerators include respective memories. In the method, a problem having 2n size is divided into a plurality of units each having 2u size. At least a part of the units is allocated to the one or more accelerators. A determination is made as to whether there is a remaining part of the units to be allocated onto the processing circuitry. A temporary buffer is prepared on each memory of at least the one or more accelerators. The temporary buffer is used for storing a copy of a dependent unit stored on a different memory, during inter-unit calculation.Type: GrantFiled: January 3, 2019Date of Patent: June 2, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: Jun Doi
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Patent number: 10642705Abstract: A storage system includes a first memory, and a processor configured to calculate a first number of accesses from a first server to the first memory and a second number of accesses from a second server to the first memory, detect switching from the first server to the second server in accordance with the first number and the second number, determine whether a first site in which the first memory is disposed and a second site in which the second server is disposed are different on the basis of location information that represents a location relationship between the first memory and the second server, and perform a change of an access destination of the second server to a second memory disposed in the second site when the first site and the second site are different.Type: GrantFiled: January 7, 2019Date of Patent: May 5, 2020Assignee: FUJITSU LIMITEDInventor: Masanori Furuya
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Patent number: 10642593Abstract: Implementations are described of a computing device that migrates data and software applications from a first computing device to a second computing device, in order to preserve data and other application-related customizations.Type: GrantFiled: December 20, 2018Date of Patent: May 5, 2020Assignee: Microsoft Technology Licensing, LLCInventors: David A. Nichols, Samuel J. McKelvie, Navjot Virk, Mathew J. Dickson
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Patent number: 10635625Abstract: A plug connector component is provided having a housing, at least one control module arranged therein and an operating system for operating the control module. At least one functional module that can be controlled by the control module can be introduced into the housing. In addition, the control module is configured to receive at least one container with at least one process configured for using an operating system core of the operating system and to implement same, and to at least partially control the functional module by the process. Related plug connectors, systems and methods are also provided.Type: GrantFiled: July 7, 2017Date of Patent: April 28, 2020Assignee: HARTING Electric GmbH & Co. KGInventors: Lutz Tröger, Christoph Gericke, Markus Friesen, Karsten Walther
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Patent number: 10620960Abstract: An apparatus and method are provided for performing branch prediction. The apparatus has processing circuitry for executing instructions out-of-order with respect to original program order, and event counting prediction circuitry for maintaining event count values for branch instructions, for use in making branch outcome predictions for those branch instructions. Further, checkpointing storage stores state information of the apparatus at a plurality of checkpoints to enable the state information to be restored for a determined one of those checkpoints in response to a flush event. The event counting prediction circuitry has training storage with a first number of training entries, each training entry being associated with a branch instruction.Type: GrantFiled: August 20, 2018Date of Patent: April 14, 2020Assignee: Arm LimitedInventors: Houdhaifa Bouzguarrou, Guillaume Bolbenes, Vincenzo Consales
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Patent number: 10606775Abstract: Systems, apparatuses, and methods related to a computing tile are described. The computing tile may perform operations on received data to extract some of the received data. The computing tile may perform operations without intervening commands. The computing tile may perform operations on data streamed through the computing tile to extract relevant data from data received by the computing tile. In an example, the computing tile is configured to receive a command to initiate an operation to reduce a size of a block of data from a first size to a second size. The computing tile can then receive a block of data from a memory device coupled to the apparatus. The computing tile can then perform an operation on the block of data to extract predetermined data from the block of data to reduce a size of the block of data from a first size to a second size.Type: GrantFiled: December 28, 2018Date of Patent: March 31, 2020Assignee: Micron Technology, Inc.Inventors: Richard C. Murphy, Glen E. Hush, Vijay S. Ramesh, Allan Porterfield, Anton Korzh
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Patent number: 10591544Abstract: Integrated circuit packages with multiple integrated circuit dies are provided. A multichip package may include a master die that is coupled to one or more slave dies via inter-die package interconnects. A mixed (i.e., active and passive) interconnect redundancy scheme may be implemented to help repair potentially faulty interconnects to improve assembly yield. Interconnects that carry normal user signals may be repaired using an active redundancy scheme by selectively switching into use a spare driver block when necessary. On the other hand, interconnects that carry power-on-reset signals, initialization signals, and other critical control signals for synchronizing the operation between the master and slave dies may be supported using a passive redundancy scheme by using two or more duplicate wires for each critical signal.Type: GrantFiled: July 23, 2018Date of Patent: March 17, 2020Assignee: Altera CorporationInventors: Dana How, Dinesh Patil, Arifur Rahman, Jeffrey Erik Schulz
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Patent number: 10592454Abstract: A system-on-chip (SoC) to perform a deadlock control on a processor of the SoC, the SoC including the processor including a plurality of central processing unit (CPU) cores, a first bus connected to the processor, a graphic processing unit (GPU) connected to the first bus, a memory controller connected to the first bus, a second bus connected to the processor, an isolation cell including a logic circuit configured to retain a signal value input to the processor according to an isolation signal, and a deadlock controller connected to the first bus and the second bus. The deadlock controller is configured to isolate the processor, which is in a deadlock state, from the first bus by applying the isolation signal on the isolation cell, and to extract, via the second bus, state information of the isolated processor in the deadlock state.Type: GrantFiled: July 13, 2018Date of Patent: March 17, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-Youl Kim, Chih Jen Lin, Jinook Song, Sungjae Lee, Hyun-ki Koo, Donghyeon Ham
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Patent number: 10592376Abstract: Real-time USB class level decoding is disclosed. In some embodiments, a first packet associated with a USB class level operation associated with a target USB device that is being monitored is received. A second packet generated by a USB hardware analyzer configured to observe USB traffic associated with the target USB device is received. It is determined based at least in part on a time associated with one or both of the first packet and the second packet that the class level operation has timed out.Type: GrantFiled: January 7, 2019Date of Patent: March 17, 2020Assignee: Total Phase, Inc.Inventors: Kumaran Santhanam, Leonid Vaynberg
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Patent number: 10592460Abstract: Methods and apparatus for virtual channel allocation within an electronic device. In one exemplary embodiment, the device is a consumer electronics device having multiple camera sensors uses a modified high-speed protocol (e.g., DisplayPort Multi-Stream Transport (MST) protocol) to process camera data via one or more virtual channels. Unlike traditional solutions which rely on an intelligent source device to manage a network of devices, the present disclosure describes in one aspect a network of nodes internal to a consumer electronic device that is managed by the sink node (i.e., a “smart sink”). Additionally, since the full suite of protocol (e.g., DisplayPort) capabilities are unnecessary for certain design scenarios, certain further disclosed simplifications improve performance for sink nodes having very modest capabilities.Type: GrantFiled: January 7, 2019Date of Patent: March 17, 2020Assignee: Apple Inc.Inventors: Colin Whitby-Strevens, Sreeraman Anantharaman
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Patent number: 10585816Abstract: An information handling system includes a planar board and a peripheral interface device. The planar board includes a central processing unit, a baseboard management controller, and an interface logic circuit. The peripheral interface device includes a microcontroller and a serial communication interface device. The peripheral interface device is coupled to a peripheral device. The information handling system also includes an interconnect to couple signals from the planar board to the peripheral interface device. The interconnect includes a single wire to couple first information from the interface logic circuit to the peripheral interface device and to couple second information from the serial communication interface device to the interface logic circuit. The first information includes a first power control command.Type: GrantFiled: December 7, 2018Date of Patent: March 10, 2020Assignee: Dell Products, L.P.Inventors: Timothy M. Lambert, Jordan Chin, Jeremiah Bartlett, Jeffrey L. Kennedy
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Patent number: 10573598Abstract: An example integrated circuit (IC) package includes: a processing system and a programmable IC disposed on a substrate, the processing system coupled to the programmable IC through interconnect of the substrate; the processing system including components coupled to a ring interconnect, the components including a processor and an interface controller. The programmable IC includes: an interface endpoint coupled to the interface controller through the interconnect; and at least one peripheral coupled to the interface endpoint and configured for communication with the ring interconnect of the processing system through the interconnect endpoint and the interface controller.Type: GrantFiled: September 28, 2017Date of Patent: February 25, 2020Assignee: XILINX, INC.Inventors: Austin H. Lesea, Sundararajarao Mohan, Stephen M. Trimberger
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Patent number: 10572405Abstract: A method of communicating messages between a plurality of modules in a system on a vehicle, each module of the plurality of modules implemented on at least one processor and configured as a publisher node and/or a subscriber node and collectively forming a plurality of nodes that communicate in the operation of the vehicle. The method may include generating a first message associated with a first topic by a first publisher node, writing, by the first publisher node, the first message in a memory location in a first message buffer of the plurality of message buffers, the first message buffer associated with the first topic and configured to store a plurality of messages associated with the first topic, and writing in a registry information associated with writing the first message, the registry configured to store location information of the first message.Type: GrantFiled: December 28, 2018Date of Patent: February 25, 2020Assignee: DiDi Research America, LLCInventors: Yuzhu Shen, Alok Priyadarshi
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Patent number: 10558464Abstract: Embodiments include load-balancing a plurality of simultaneous threads of a processor. An example method includes computing a minimum group count for a thread from the plurality of threads. The minimum group count indicates a minimum number of groups of instructions to be assigned to the thread. The method further includes computing a maximum allowed group count for the thread. The maximum allowed group count indicates a maximum number of groups of instructions to be assigned to the thread. The method further includes issuing one or more groups of instructions for execution by the thread based on the minimum group count and the maximum allowed group count for the thread.Type: GrantFiled: February 9, 2017Date of Patent: February 11, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Gregory W. Alexander, Stephen Duffy, David S. Hutton, Christian Jacobi, Anthony Saporito, Somin Song
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Patent number: 10552352Abstract: Methods and apparatus for a synchronized multi-directional transfer on an inter-processor communication (IPC) link. In one embodiment, the synchronized multi-directional transfer utilizes one or more buffers which are configured to accumulate data during a first state. The one or more buffers are further configured to transfer the accumulated data during a second state. Data is accumulated during a low power state where one or more processors are inactive, and the data transfer occurs during an operational state where the processors are active. Additionally, in some variants, the data transfer may be performed for currently available transfer resources, and halted until additional transfer resources are made available. In still other variants, one or more of the independently operable processors may execute traffic monitoring processes so as to optimize data throughput of the IPC link.Type: GrantFiled: August 6, 2018Date of Patent: February 4, 2020Assignee: Apple Inc.Inventors: Karan Sanghi, Vladislav Petkov, Radha Kumar Pulyala, Saurabh Garg, Haining Zhang
