Abstract: A discharge circuit integrated in a chip of a slave device to follow a bus rectifier bridge includes: a digital control module for generating, when an output result of a comparator is that a bus voltage falls, a high-level and time-configurable pulse width to drive a discharge circuit to discharge a bus; a discharge current source module for enabling the discharge of the bus by means of a digital control module and adjusting a discharge current; a comparator for obtaining a status of a change in the bus voltage; and a peripheral circuit for monitoring the change in the bus voltage, providing to the comparator a voltage signal which reflects divided bus voltage fall information, and generating a comparison reference voltage.

Abstract: Techniques for configuring a system may include selecting one of a plurality of I/O slots to be allocated a number of lanes connected to a processor; and responsive to selecting the one I/O slot, sending a selection signal to a multiplexer that selects the one I/O slot from the plurality of I/O slots and configures the number of lanes for use by the one I/O slot where the number of lanes connect the one I/O slot to the processor. The system may be a data storage system and the lanes may be PCIe lanes used for data transmission. For each I/O slot, an I/O module may be inserted, removed or replaced (e.g., removed and then replaced with a new I/O card). A management controller may select the one I/O slot and send the selection signal in accordance with one or more policies. The system may support hot plug I/O modules.

Abstract: A unit is connected to both devices to be controlled and the other unit. The unit includes a control unit connected to the devices to be controlled, and a shared memory to be capable of storing therein information. The control unit allocates control data related to the devices to be controlled to the shared memory of its own unit and the shared memory of the other unit so as to be stored respectively in the shared memories.

Abstract: A method for accelerating distributed stream processing. The method includes allocating a hardware accelerator to a topology for distributed stream processing. The topology includes a spout and a plurality of bolts. The spout is configured to prepare a plurality of tuples. The plurality of bolts are configured to process the plurality of tuples and include at least one proxy bolt. The proxy bolt is configured to perform a proxy operation on an input tuple of the plurality of tuples. The method further includes obtaining a customized hardware accelerator by customizing the hardware accelerator based on the proxy operation, sending the input tuple from the proxy bolt to the customized hardware accelerator, generating an output tuple of the plurality of tuples by performing the proxy operation on the input tuple in the customized hardware accelerator, and sending the output tuple from the customized hardware accelerator to the proxy bolt.

Abstract: Embodiments of a multi-processor array are disclosed that may include a plurality of processors and configurable communication elements coupled together in a interspersed arrangement. Each configurable communication element may include a local memory and a plurality of routing engines. The local memory may be coupled to a subset of the plurality of processors. Each routing engine may be configured to receive one or more messages from a plurality of sources, assign each received message to a given destination of a plurality of destinations dependent upon configuration information, and forward each message to assigned destination. The plurality of destinations may include the local memory, and routing engines included in a subset of the plurality of configurable communication elements.

Abstract: A method of scheduling a system-on-chip (SoC) by a scheduler, located between a plurality of masters and a slave, includes receiving a plurality of access requests from the plurality of masters, setting the plurality of access requests in a plurality of registers, and scheduling the plurality of access requests based on the plurality of access requests.

Abstract: A system comprising a plurality of functional modules connected by a bus, each functional module comprising a photo emitter and a photo receiver, to transmit photo signals between two adjacent modules. A method for addressing the functional modules, wherein a control module broadcasts respective unique addresses to the bus and a photo enquiry signal to its downstream module to trigger the latter to pick up an address. Each module provides a photo enquiry signal to its downstream module, after it has picked up an address from the bus.

Abstract: A processor circuit and an operation method thereof are provided. The processor circuit includes a re-order buffer (ROB) and an alias queue (AQ) module. The ROB records next sequential instruction pointer (Nsip) values of a plurality of load instructions and a plurality of store instructions. Each of a plurality of entries of the AQ module includes a first field and a plurality of second fields. When a first load instruction and a first store instruction cause a first memory violation and the ROB retires the first load instruction, the AQ module stores the Nsip value of the first load instruction into the first field of one of the entries and stores the Nsip value of the first store instruction into one of the second fields of one of the entries.

Abstract: Each of one or more storage device units has a switch device for relaying communication in accordance with a communication interface in which the number of master devices that can exist in the same domain is defined and having a plurality of switch ports. A controller unit has a storage controller having a plurality of initiator ports. A storage controller acquires, via each of the plurality of initiator ports, the ID of a storage device unit connected to the initiator port. The storage controller determines a system configuration on the basis of a port ID relationship between the plurality of initiator ports and the plurality of acquired IDs. The storage controller performs switch setting, for each of the one or more switch devices, that corresponds to the determined system configuration, via at least one initiator port connected to the switch device.

Abstract: Described are techniques for processing I/O operations that may include: issuing, by a process of an application on a host, an I/O operation; tagging the I/O operation with a tag value in accordance with a process name associated with the process that issued the I/O operation; sending the I/O operation from the host to a data storage system; and determining, on the data storage system, an service level objective (SLO) for the I/O operation in accordance with the tag value of the I/O operation. The process name may include a first portion and a second customizable or configurable portion used to distinguish between different instance of the same application process. It may be determined which of multiple time-dependent SLOs for the process name is active and used with the I/O operation based on a receipt or processing time associated with the I/O operation.

Abstract: The invention provide an application specific instruction-set processor (ASIP) that uses a Very Long Instruction Word (VLIW) for executing atomic application specific instructions. The ASIP includes one or more units for executing a first set of atomic application specific instructions for receiving a first set of data across a plurality of input data ports in a first operation specified in an instruction word. Further, the one or more units execute a second set of atomic application specific instructions for outputting a second set of data across a plurality of output data ports in a second operation specified in the instruction word, wherein an input data port of the plurality of input data ports and a corresponding output data port of the plurality of output data ports share a same address location and are specified as operands in the instruction word. Thus, the first operation and the second operation can occur simultaneously.

Abstract: Systems, methods, and apparatuses relating to a memory fence mechanism in a configurable spatial accelerator are described. In one embodiment, a processor includes a plurality of processing elements and an interconnect network between the plurality of processing elements to receive an input of a dataflow graph comprising a plurality of nodes, wherein the dataflow graph is to be overlaid into the interconnect network and the plurality of processing elements with each node represented as a dataflow operator in the plurality of processing elements, and the plurality of processing elements are to perform a plurality of operations, each by a respective, incoming operand set arriving at each of the dataflow operators of the plurality of processing elements. The processor also includes a fence manager to manage a memory fence between a first operation and a second operation of the plurality of operations.

Abstract: An accelerator manager manages multiple accelerators in multiple programmable devices. An accelerator cast out policy specifies criteria for casting out accelerators in the programmable devices. The accelerator manager monitors usage of the accelerators by one or more computer programs, and generates a historical log from the monitored usage. When the conditions in the historical log satisfy criteria in the accelerator cast out policy for casting out an accelerator, the accelerator manager casts out the accelerator, and updates a virtual function table to replace calls to the accelerator that was cast out with calls to the software library.

Abstract: An apparatus includes an interface and a plurality of impedance branches. The interface may be configured to receive a data signal and a plurality of selection signals. The plurality of impedance branches may comprise a group of branches and a separated branch. The plurality of impedance branches may be configured to adjust an impedance value and a gain of a data path for the data signal in response to the selection signals. The group of branches may be controlled in response to the selection signals to select the impedance value and a first gain value in a first mode. The separated branch may replace one of the plurality of impedance branches in the group of branches in response to the selection signals to select a second gain value in a second mode.

Abstract: A storage apparatus accessed by using a memory bus is disclosed. The apparatus includes an interface controller, a storage module, a storage controller, a command register, a status register, and a buffer. In addition, the interface controller can be electrically connected to a memory module interface of a computer system. The interface controller receives an access command for accessing the storage module sent by a CPU. The interface controller writes the access command into the command register, and records a current access status or result by using the status register. The storage controller performs status setting on the status register according to the access command in the command register, and performs a corresponding read/write operation on the storage module.

Abstract: A computer includes a first module, a second module controlled by the first module, a first connector connectable to the first module, a second connector connectable to either the first module or the second module, and a data transmission line configured to connect the first connector to the second connector. The first module includes a switch configured to electrically connect the data transmission line to the first module attached to the first connector. The switch breaks an electrical connection between the data transmission line and the first module attached to the second connector. Thus, it is possible to improve expandability in the computer acting as a server. Additionally, it is possible to prevent complexity of design and increased cost in manufacturing servers.

Abstract: Provided is an electronic device including a semiconductor memory.

Abstract: A hub including a first connection interface, a second connection interface, and a signal bypass circuit is provided. The first connection interface has a first pin to receive a first connection message. The second connection interface has a second pin to transmit the first connection message. The signal bypass circuit is coupled to the first pin and the second pin to decide whether to bypass the first pin and the second pin based on the first connection message.

Abstract: A control method includes: making, by a transmitting apparatus coupled to an information processing apparatus and provided in the transmission and reception system where the transmitting apparatus and a receiving apparatus coupled to an input and output apparatus are coupled with each other through a network, a response to the information processing apparatus in response to a first command received from the information processing apparatus; obtaining, by the transmitting apparatus, a commands from the information processing apparatus after receiving the first command; batch-transferring the commands to the receiving apparatus without making a response to the information processing apparatus; issuing, by the receiving apparatus, the commands transferred from the transmitting apparatus to the input and output apparatus; and notifying, by the receiving apparatus, when the commands is batch-transferred from the transmitting apparatus, the transmitting apparatus about processing completion when processing of all o

Abstract: Systems, methods, and apparatus for communication virtualized general-purpose input/output signals over a serial communication link A method performed at a transmitting device coupled to a communication link includes configuring general-purpose input/output (GPIO) state from a plurality of sources into a virtual general-purpose input/output word, identifying one or more destinations for the first GPIO word based on a mapping of the GPIO state to one or more devices coupled to a serial bus, and transmitting the first GPIO word to each destination.