Abstract: A semiconductor memory device comprises: a memory cell array having a standard memory cell array part in which dynamic memory cells are arranged in a matrix pattern, and a redundant memory cell array having a redundant memory cell set up to replace a defective memory cell in the standard memory cell array part; an access control part controlling external access operation and refresh access operation regarding the memory cell array; and a redundancy judgment circuit executing redundancy judgment to determine whether the memory cell which is a subject to the external access operation or the refresh access operation is the redundant memory cell or not, controlling so as to access the redundant memory cell, if the subjected memory cell is the redundant memory cell, and controlling so as to access the memory cell in the standard memory cell array, if the subjected memory cell is not the redundant memory cell.

Abstract: Bit lines (BL0, BL0R, BL1, BL1R, . . . ) of a ROM memory array with differential detection reading are arranged within two overlaid metallization levels so as to increase the read reliability of binary values stored in the array. The ROM array is divided into matrix segments (100, 101, . . . ) aligned parallel to the bit lines. The bit lines are shifted horizontally and/or vertically within transition regions (T) located between the segments of matrix, by effecting circular permutations between the positions of the bit lines that are divided up into groups of four.

Abstract: A method is described for erasing a selected data region in an NROM cell that is a member of a virtual ground NROM EEPROM array. The method provides that erasing the selected data region does not disturb the program state of unselected data regions.

Abstract: An integrated circuit (IC) includes a redundancy feature. The redundancy feature is provided by a redundancy circuitry within the IC. The redundancy circuitry is configured to provide the redundancy by using a decoder circuitry. The decoder circuitry receives and decodes coded defect information from a set of circuit elements adapted to provide the coded defect information.

Abstract: A memory array includes a buried diffusion region, a first source line that supplies electrical power to the buried diffusion region, a second source line that supplies electrical power to the buried diffusion region, a first bitline transistor having a first channel width and a second bitline transistor having a second channel width. The first bitline transistor is proximate to the first source line and is electrically coupled to a first memory cell. The first bitline transistor is disposed between the first and second source lines. The second bitline transistor is proximate to the first bitline transistor and is electrically coupled to a second memory cell. The second bitline transistor is disposed between the first and second source lines and is farther from the first source line than the first bitline transistor. The second channel width is greater than the first channel width.

Abstract: The programming speed of a nonvolatile semiconductor memory device used as a flash memory is increased as follows. First, second, and third assist gates, a control gate, as well as first and second storage nodes are created over a p-type well. In the course of a programming operation, first of all, the p-type well is set at 0V. Then, a first inversion layer created by setting the first assist gate at a voltage A is set at a voltage B and the second assist gate is set at a voltage C. Subsequently, a second inversion layer created by setting the third assist gate at a voltage D is set at a voltage E and the control gate is set at a voltage F to inject hot electrons generated on the surface of the p-type well in close proximity to the second assist gate into the second storage node.

Abstract: A step voltage generator includes multiple trainable voltage references. Each of the trimmable voltage references uses a flash cell with a variable threshold voltage and a feedback loop to trim a reference voltage. The threshold voltage of the flash cell can be programmed to affect the reference voltage.

Abstract: A dynamic programming method for a non-volatile storage device is described. Memory cells are provided arrayed in R rows. Sub bit lines are provided coupled to voltage supply lines through select circuits. During program operation, the select circuits are switched such that one or more of the source side sub bit line or the drain side sub bit line is floating when all other program voltages are applied to a selected cell.

Abstract: Disclosed is an input data distribution device for a memory device, the input data distribution device comprising: a decoding section for receiving a starting column address applied when a write command is activated; and N number of switching sections each of which receives N bits of data applied sequentially through one data pin after the write command is activated, wherein each of the switching sections exclusively outputs one bit from among the N bits of data by using an output signal of the decoding section and a signal for determining a burst type.

Abstract: A nonvolatile memory device, including a plurality of memory cell blocks, N memory cell blocks (N is an integer equal to or greater than 2) being arranged in a row direction, L memory cell blocks (L is an integer equal to or greater than 2) being arranged in a column direction, and each of the memory cell blocks including M memory cells (M is an integer equal to or greater than 2), a plurality of wordlines, a plurality of first control gate lines, a plurality of first control gate switches, a plurality of second control gate lines, and a plurality of bitlines.

Abstract: A self-refresh module includes an oscillator configured to provide a first signal having a first frequency, a trimming divider configured to trim the first signal to provide a second signal having a second frequency, and a temperature sensor configured to sense a temperature of the memory device and provide a temperature signal. The self-refresh module includes a temperature look-up table configured to receive the temperature signal and provide a third signal based on the temperature signal, and a temperature divider configured to provide a self-refresh pulse signal based on the second signal and the third signal.

Abstract: A semiconductor memory device includes a word drive line, and a word line connected with memory cells. A first drive circuit drives the word drive line to a first voltage based on a main word signal, and resets the word drive line to a ground voltage in a time period for transition of an address signal. A second drive circuit outputs a signal of the first voltage to the word line based on a sub-word signal such that a data is read out from one of the memory cells. The main word signal and the sub-word signal are obtained from an address signal, and are signals taking the ground voltage or a second voltage which is lower than the first voltage.

Abstract: The present invention relates to an electronic device comprising a memory cell with a resistive storage element having a first terminal and a second terminal. The resistive storage element can be switched between a first storage state with a first conductivity and a second storage state with a second conductivity. An access switch is coupled to the first terminal of the resistive storage element and to a node for connecting the first terminal of the resistive storage element to the node in an access state of the memory cell and for insulating the first terminal of the resistive storage element from the node in an idle state of the memory cell. A protecting switch is connected to the resistive storage element. The protecting switch, in the idle state of the memory cell, reduces the voltage across the resistive storage element produced by electromagnetic interference and, in the access state of the memory cell, enables the reading and the writing of the storage states of the resistive storage element.

Abstract: A method and apparatus for minimizing errors that may occur when writing information to a magnetic memory cell array with an operating write current due to changes in the local magnetic fields and. A test write current is sent to a reference memory cell and the effect of the test current on the orientation of the magnetization in the reference cell is monitored. The write current is then modified to compensate for any changes in the optimum operating point that have occurred. Arrays of reference magnetic memory cells having varying properties may be used to more accurately characterize any changes that have occurred in the operating environment. A phase difference between a time varying current used to drive the reference cell and the corresponding variations in the orientation of the magnetization in the reference cell may also be used to further characterize changes in the operating environment.

Abstract: A semiconductor memory device able to read out data at a high speed continuously, provided with, corresponding to a plurality of banks, current address registers for holding addresses for reading data of cell arrays, reserved address registers able to receive in advance and hold reserved addresses for next read operations from the outside, and bank control circuits for making the current address registers hold reserved addresses held in the reserved address registers, making the data be read out, and making the data latch circuits hold the data when the data read out from the cell arrays of the banks by addresses held in the current address registers and held in the data latch circuits become able to be transferred to the outside, and a signal processing system relating to the same.

Abstract: A method and system is disclosed for a wordline driver circuit used for a memory device. It has a logic stage operating between a ground voltage and a first supply voltage and generating a logic stage output signal swinging between the ground voltage and the first supply voltage. It also has a mid voltage stage, operating between a raised ground voltage and a second supply voltage during the programming process, and generating a mid voltage stage output that swings between the second supply voltage and the raised ground voltage. It then has a high voltage stage, operating between the raised ground voltage and a third supply voltage, and generating a wordline driver output swinging between the third supply voltage and the raised ground voltage based on the received mid voltage stage output.

Abstract: A method and circuitry for alleviating the adverse effect of variable read decode propagation delays and variable output circuitry propagation delays on the read latency, and specifically for generating output enable signals at an appropriate time in light of such variable delays, is disclosed. In one embodiment, a first time domain as specified by an internal clock is delayed by the propagation delay of the read decoder block plus the propagation delay of the output circuitry via a model to create a second time domain which lags the first time domain. Processing in the second time domain associates the internal read command with a particular external clock cycle, and accounts for the specified read latency of the device. The output of such second time domain processing is a signal indicative of which external cycle should be used to enable the outputs. This signal is then converted back into the first timing domain by latches which lead the second timing domain.

Abstract: Disclosed is a voltage dividing circuit reducing effects of a parasitic capacitance and a wordline voltage generating circuit including that. The voltage dividing circuit according to an aspect of the present invention includes a first resistor, a plurality of second resistors, and a selection means. The first resistor is connected between an output voltage node and a dividing voltage node. The plurality of second resistors are connectable between the dividing voltage node and a ground. The second resistors are sequentially selected in response to a step control signal and connected to ground. In order to reduce the sum of a parasitic capacitance existing in the second resistors, the resistors are arranged in groups, and the selection means connects only that group that contains a selected resistor to the dividing voltage node.

Abstract: Disclosed are a method of controlling a page buffer having a dual register and a control circuit thereof. In the present invention, during a normal program operation, a normal program operation is performed through the same transmission path as a data transmission path along which data is outputted from bit lines of a memory cell array to a YA pad according to a signal PBDO used in a read operation. A program operating time can be reduced and the whole program operation of a chip can be thus reduced. It is also possible to reduce current consumption by shortening a data path during the normal program operation.

Abstract: A semiconductor memory device is provided comprising precharge circuits corresponding to global data line pairs, but not a precharge circuit corresponding to a local data line pair. In a command waiting state, data line selection switches are controlled to be in a connected state, so that the local data line pair and the global data line pairs are precharged all together while being connected to each other. In a command executing state, one of the data line selection switches, the one being not required for command execution, is in an open state. Similarly, a semiconductor memory device comprising only a precharge circuit corresponding to a local data line pair can be provided.