Abstract: A structure is disclosed, comprising: a first field effect transistor, FET, comprising a first source terminal, a first drain terminal, a first layer or body of semiconductive material arranged to provide a first semiconductive channel connecting the first source terminal to the first drain terminal, and a gate terminal arranged with respect to the first semiconductive channel such that a conductivity of the first semiconductive channel may be controlled by application of a voltage to the gate terminal; and a second FET comprising a second source terminal, a second drain terminal, a second layer or body of semiconductive material arranged to provide a second semiconductive channel connecting the second source terminal to the second drain terminal, and the gate terminal, the second conductive channel being arranged with respect to the gate terminal such that a conductivity of the second channel may be controlled by application of a voltage to the gate terminal.

Abstract: A semiconductor device includes a substrate; a memory array over the substrate, the memory array including first magnetic tunnel junctions (MTJs), where the first MTJs are in a first dielectric layer over the substrate; and a resistor circuit over the substrate, the resistor circuit including second MTJs, where the second MTJs are in the first dielectric layer.

Abstract: A surface mountable light emitting diode (LED) package with inclined light emitting surface is presented herein. An optoelectronic component comprises the surface mountable package, which comprises a top surface, a cavity, and a mounting surface that is parallel to the top surface to facilitate an attachment, via an automatic surface mount technology pick-and-place equipment, of the mounting surface to a printed circuit board of the optoelectronic component. The cavity comprises a material that facilitates a transmission of electromagnetic radiation comprising visible light and infrared light, optoelectronic device(s) positioned within the cavity that generate and/or receive the electromagnetic radiation, and a light emitting surface that is adjacent to the top surface and that is inclined at an angle relative to a vertical axis of a plane of the top surface to facilitate, via the material, a transmission/reception of the electromagnetic radiation from/by the optoelectronic device(s).

Abstract: A package structure including a semiconductor die, a redistribution layer, a plurality of antenna patterns, a die attach film, and an insulating encapsulant is provided. The semiconductor die have an active surface and a backside surface opposite to the active surface. The redistribution layer is located on the active surface of the semiconductor die and electrically connected to the semiconductor die. The antenna patterns are located over the backside surface of the semiconductor die. The die attach film is located in between the semiconductor die and the antenna patterns, wherein the die attach film includes a plurality of fillers, and an average height of the die attach film is substantially equal to an average diameter of the plurality of fillers. The insulating encapsulant is located in between the redistribution layer and the antenna patterns, wherein the insulating encapsulant encapsulates the semiconductor die and the die attach film.

Abstract: Various embodiments include combined lens and safety enclosure apparatuses and methods for forming the apparatuses. In one example a combined lens and safety enclosure apparatus for a light-emitting diode (LED) module is disclosed. The enclosure apparatus includes at least one plastic-material-based optical-lens element mounted over a plurality of LED elements, where a distance between the optical-lens element and any portion of any one of the plurality of LED elements is spaced away from each other by at least 0.8 mm. A driver-on-board (DoB) subsystem, including an electronic circuit configured to provide power to the plurality of LED elements, has a plastic-material-based optical enclosure mounted over the DoB subsystem. A distance between the optical enclosure and any portion of any of the electronic circuit is spaced away from optical enclosure by at least 0.8 mm. Other devices and methods are described.

Abstract: A method for manufacturing a semiconductor device and a semiconductor device produced thereby. For example and without limitation, various aspects of this disclosure provide methods for manufacturing a semiconductor device, and semiconductor devices produced thereby, that comprise forming an interposer including a reinforcement layer.

Abstract: A packaged semiconductor device includes a molded interconnect substrate having a signal layer including a first channel and a second channel on a dielectric layer with vias, and a bottom metal layer for providing a ground return path. The signal layer includes contact pads, traces of the first and second channel include narrowed trace regions, and the bottom metal layer includes a patterned layer including ground cut regions. DC blocking capacitors are in series within the traces of the first and second channel for providing AC coupling that have one plate over one of the ground cuts. An integrated circuit (IC) includes a first and a second differential input channel coupled to receive an output from the DC blocking capacitors, with a bump array thereon flip chip mounted to the contact pads to provide first and second differential output signals.

Abstract: A method for manufacturing a light-emitting device includes: forming a cover, which comprises: sandwiching a fixing member by a molding device, injecting a light-transmissive material into a space defined in the molding device, and hardening or curing the injected light-transmissive material, wherein the formed cover comprises an upper portion, a sidewall, and a recess, the cover being integrated with the fixing member such that the fixing member projects from a part of an outer lateral surface of the sidewall; disposing a light-transmissive member on a light extraction surface of a light-emitting element to be disposed on a substrate; and disposing the cover so that the light-emitting element is housed in the recess. The fixing member is formed of a material that is deformable due to a pressing force generated in the event of an engagement with a counterpart member.

Abstract: Interconnect structures and method of forming the same are disclosed herein. An exemplary interconnect structure includes a first contact feature in a first dielectric layer, a second dielectric layer over the first dielectric layer, a third dielectric layer over the second dielectric layer, a second contact feature extending through the second dielectric layer and the third dielectric layer, and a graphene layer between the second contact feature and the third dielectric layer.

Abstract: Generally discussed herein are systems, devices, and methods to reduce crosstalk interference. An interconnect structure can include a first metal layer, a second metal layer, a third metal layer, the first metal layer closer to the first and second dies than the second and third metal layers, the first metal layer including a ground plane within a footprint of a bump field of the interconnect structure and signal traces outside the footprint of the bump field.

Abstract: Described herein are one or more methods for integrating an optical component into an integrated photonics device. The die including a light source, an outcoupler, or both, may be bonded to a wafer having a cavity. The die can be encapsulated using an insulating material, such as an overmold, that surrounds its edges. Another (or the same) insulating material can surround conductive posts. Portions of the die, the overmold, and optionally, the conductive posts can be removed using a grinding and polishing process to create a planar top surface. The planar top surface enables flip-chip bonding and an improved connection to a heat sink. The process can continue with forming one or more additional conductive layers and/or insulating layers and electrically connecting the p-side and n-side contacts of the laser to a source.

Abstract: In a method of forming a semiconductor device, a plurality of transistor pairs is formed to be stacked over a substrate. The plurality of transistor pairs have a plurality of gate electrodes that are stacked over the substrate and electrically coupled to gate structures of the plurality of transistor pairs, and a plurality of source/drain (S/D) local interconnects that are stacked over the substrate and electrically coupled to source regions and drain regions of the plurality of transistor pairs. A sequence of vertical and lateral etch steps are performed to etch the plurality of the gate electrodes and the plurality of S/D local interconnects so that the plurality of the gate electrodes and the plurality of S/D local interconnects have a staircase configuration.

Abstract: A semiconductor device includes a field effect transistor (FET). The FET includes a first channel, a first source and a first drain; a second channel, a second source and a second drain; and a gate structure disposed over the first and second channels. The gate structure includes a gate dielectric layer and a gate electrode layer. The first source includes a first crystal semiconductor layer and the second source includes a second crystal semiconductor layer. The first source and the second source are connected by an alloy layer made of one or more Group IV element and one or more transition metal elements. The first crystal semiconductor layer is not in direct contact with the second crystal semiconductor layer.

Abstract: A light emitting diode (LED) package structure include an electrically-insulated frame, a trough, a LED chip, a fluorescent colloid and at least two spacing members. The electrically-insulated frame has a surface with four corners. The trough is recessed in the surface. The LED chip is located in the trough. The fluorescent colloid is filled within the trough to cover the LED chip. The spacing members protrude from two of the four corners on the surface, wherein a glue escape gap is defined between each spacing member and a boundary of the trough.

Abstract: The present invention relates to a process for manufacturing an optoelectronic device, wherein a layer of a formulation containing a silazane polymer and a wavelength converting material is applied to an optoelectronic device precursor, precured by exposure to radiation and then cured. There is further provided an optoelectronic device, preferably a light emitting device (LED) or a micro-light emitting device (micro-LED), which is prepared by said manufacturing process.

Abstract: A display device may include a substrate. A first light emitting element is disposed on the substrate. A second light emitting element is disposed on the substrate and is positioned adjacent to the first light emitting element. A first encapsulation layer is disposed on the first light emitting element and the second light emitting element. A light path control layer is disposed on the first encapsulation layer. The light path control layer includes a first pattern overlapping the first light emitting element and having a first refractive index and a second pattern overlapping the second light emitting element and having a second refractive index that is greater than the first refractive index.

Abstract: A light emitting device includes: a light emitting element; a wavelength conversion member including: a wavelength conversion portion arranged on or above an upper surface of the light emitting element, and a light-transmissive portion, wherein, in a plan view, the light-transmissive portion surrounds at least one or more lateral surfaces of the wavelength conversion portion; a sealing member comprising a lens portion that is arranged on or above an upper surface of the wavelength conversion member; and a light reflection member that surrounds one or more lateral surfaces of the wavelength conversion member. In a plan view, the wavelength conversion member is inside a perimeter of the lens portion.

Abstract: A memory device includes a word line, a bit line, an active region and a bit line contact structure. The word line is disposed in the substrate, and extends along a first direction. The bit line is disposed over the substrate, and extends along a second direction. The active region is disposed in the substrate, and extends along a third direction. The bit line contact structure is disposed between the active region and the bit line. A top view pattern of the bit line contact structure has a long axis. An angle between the extending direction of this long axis and the third direction is less than an angle between the extending direction of this long axis and the first direction, and is less than an angle between the extending direction of this long axis and the second direction.

Abstract: A conductive gate over a semiconductor fin is cut into a first conductive gate and a second conductive gate. An oxide is removed from sidewalls of the first conductive gate and a dielectric material is applied to the sidewalls. Spacers adjacent to the conductive gate are removed to form voids, and the voids are capped with a dielectric material to form air spacers.

Abstract: A semiconductor device assembly includes a substrate and a die coupled to the substrate. The die includes a first contact pad electrically coupled to a first circuit on the die including at least one active circuit element, and a second contact pad electrically coupled to a second circuit on the die including only passive circuit elements. The substrate includes a substrate contact electrically coupled to both the first and second contact pads. The semiconductor device assembly can further include a second die including a third contact pad electrically coupled to a third circuit on the second die including at least a second active circuit element, and a fourth contact pad electrically coupled to a fourth circuit on the second die including only passive circuit elements. The substrate contact can be electrically coupled to the third contact pad and electrically disconnected from the fourth contact pad.