Abstract: A bit line sense amplifier includes a differential amplifier configured to receive an input signal from a bit line through an input terminal of the bit line sense amplifier and output a first signal to a first node of the bit line sense amplifier, a sensing inverter configured to receive the first signal and output a second signal to a second node of the bit line sense amplifier, the second signal resulting from inverting the first signal, a first switch configured to electrically connect the second node to a positive input of the differential amplifier, a second switch configured to electrically connect the first node to the positive input of the differential amplifier, and a third switch configured to electrically connect the second node to a negative input of the differential amplifier.

Abstract: An SRAM cell includes a first pass gate transistor connected with a first word-line and a local bit-line, a first inverter that includes an output terminal connected with the first pass gate transistor and an input terminal, a second inverter that includes an input terminal connected with the first pass gate transistor and an output terminal, a second pass gate transistor connected with a second word line, the input terminal of the first inverter and the output terminal of the second inverter, and a complementary local bit-line, a first transistor connected with the second pass gate transistor, a local computing line, and a ground electrode, and a second transistor connected with a third word-line, the local computing line, and the ground electrode.

Abstract: Disclosed is a memory chip including a plurality of first power pads and a first bus. The first bus is connected to the first power pads. One of the first power pads is coupled to the first bus via a switch device. A data width of the memory chip is determined according to a conduction state of the switch device.

Abstract: A storage device including a non-volatile memory for storing data, a temperature sensor having resistance that changes according to temperature of the temperature sensor, and a temperature measurement circuit including a plurality of transistors, which are turned on or off based on a current of the temperature sensor and have different threshold voltages from one another. The temperature management circuit may be configured to apply a current to the temperature sensor and generate information indicating the temperature of the temperature sensor or indicating damage to the temperature sensor based on an output current obtained from the plurality of transistors.

Abstract: Disclosed is a computing-in-memory device, which includes a memory cell array including an analog multiplication unit that performs a multiply-accumulate (MAC) operation on a pre-stored weight and a first analog voltage corresponding to multi-bit input data, and a driver that applies the multi-bit input data to the analog multiplication unit, and the analog multiplication unit includes a digital-to-analog converter that converts the multi-bit input data into the first analog voltage.

Abstract: Systems and methods for operating a memory include a sensing circuitry connected to a memory cell through an address decoder, a precharge circuitry configured to be connected to the sensing circuitry during a precharge stage and at least partially disconnected from the sensing circuitry during a sensing stage immediately following the precharge stage, and a reference voltage provided to the precharge circuitry, wherein the reference voltage is mirrored to the memory cell by mirroring a current flowing from the precharge circuitry with a current flowing from the sensing circuitry during the precharge stage.

Abstract: The present disclosure discloses determining, by a first device, an access key pair associated with encrypted content, the access key pair including a content access public key and a content access private key; receiving, by the first device, a public key associated with a second device; encrypting, by the first device, the content access private key based at least in part on utilizing the content access private key and the public key associated with the second device; and transmitting, by the first device, the encrypted content access private key to enable the second device to access the encrypted content. Various other aspects are contemplated.

Abstract: A semiconductor integrated-circuit (IC) chip comprises a memory cell including: a latch circuit comprising first and second inverters coupling to each other, a first latch node coupling to an input point of the first inverter and an output point of the second inverter and a second latch node coupling to an input point of the second inverter and an output point of the first inverter; a first N-type MOS transistor having a first terminal coupling to the first latch node, a second terminal coupling to a first output point of the memory cell, and a first gate terminal for controlling coupling between the first latch node and the first output point of the memory cell; a second N-type MOS transistor having a third terminal coupling to the second latch node, a fourth terminal coupling to a second output point of the memory cell, and a second gate terminal for controlling coupling between the second latch node and the second output point of the memory cell; and a P-type MOS transistor having a fifth terminal coupling

Abstract: The present invention extends to methods, systems, and computer program products for identifying and consenting to permissions for workflow and code execution. Aspects of the invention can be used to automatically scan a workflow or code definition to identify (potentially all) the actions/triggers a workflow or program intends to perform on behalf of a user. The user is shown the actions/triggers the workflow or program intends to perform (e.g., at a user interface) before consent to perform the actions/triggers is granted. As such, a user is aware of intended actions/triggers of a workflow or program before granting consent. Further, since actions/triggers are identified from the workflow or code definition (and not formulated by an author), permission requests better align with permissions that workflow or program functionality actually uses during execution.

Abstract: Circuits, systems, and methods are described herein for generating a boost voltage for a write operation of a memory cell. In one embodiment, a boost circuit includes a first inverter and a second inverter, each configured to invert a write signal. The boost circuit also includes a transistor and a capacitor. The transistor is coupled to an output of the first inverter. The transistor is configured to charge a capacitor based on the write signal and provide a supply voltage to a write driver. The capacitor is coupled to an output of the second inverter. The capacitor is configured to generate and provide a delta voltage to the write driver.

Abstract: A memory device includes: a plurality of page buffers connected a plurality of bit lines and configured to selectively precharge the bit lines, and a control circuit configured to: perform a first verify operation by applying a precharge voltage to a first bit line among the bit lines according to program data and by applying a first verify voltage to a selected word line, perform a second verify operation, after the first verify operation, by applying the precharge voltage to a second bit line not overlapping the first bit line and by applying a second verify voltage to the selected word line, and perform at least one of an operation of floating the first bit line and an operation of applying the precharge voltage according to a threshold voltage of a memory cell connected to the first bit line during the second verify operation.

Abstract: The present disclosure provides an anti-fuse type one-time programmable memory cell. The memory cell includes a selection transistor and a gate capacitor, which are connected in series and located in a substrate, the substrate including an active region and an isolation region; in which the gate capacitor includes a gate, a gate oxide layer between the gate and the substrate, and an ion-doped region beneath the gate oxide layer, the ion-doped region being located in the active region in the substrate and overlapping with a part of a lower surface of the gate oxide layer; in which a part of the lower surface of the gate oxide layer that does not overlap with the ion-doped region completely overlaps with the isolation region in the substrate, and the ion-doped region and the isolation region are seamlessly adjacent to each other in the substrate beneath the gate oxide layer.

Abstract: A method in accordance with the invention includes: providing to a hub, from an enclave associated with a TEE at a node, an enclave public key; establishing a channel with the hub by broadcasting to a blockchain network a funding transaction which encumbers a digital asset with a first public key, a second public key and a third public key such that the encumbrance of the digital asset may be removed by: 1) both a first signature generated from a first private key corresponding to the first public key and a second signature generated from a second private key corresponding to the second public key; or 2) a third signature, valid for the third public key, the third public key associated with a group; receiving a commitment transaction encrypted with the enclave public key; detecting a failure; issuing a failsafe activation request to the group using data from the enclave.

Abstract: The invention includes a UI that allows addition of functional placeholders to an AI pipeline, and a rules engine that chooses pipeline objects during or before AI pipeline execution. The rules engine can select pipeline objects meeting the same function type and object rules of the functional placeholder. The rules engine also applies customizable security rules and artificial intelligence (AI) model routing to queries. Remedial actions are taken when the rule evaluation exceeds a threshold. The remedial actions include transforming the query by replacing sensitive information with a reversible placeholder. The actual result can be modified by reversing the placeholder and redacting additional sensitive information. The system can notify the user, an administrator, and a supervisor regarding the security evaluation and remedial actions. The evaluations can be logged for auditing purposes.

Abstract: A sending device may send data intended for a target device. An intermediate device may intercept the data sent from the sending device and forward the communications to the target device. Security data (e.g., a security certificate for authentication) along with an encrypted version of the security data may be sent at the application layer such that it passes from the sending device, through the intermediate device, and to the target device without being analyzed or modified by the intermediate device. The target device may use the encrypted security data and the security data to verify the identity of the sending device.

Abstract: In some example embodiments, there is provided a method, which includes sending a message to a server, wherein the message includes a request for a share code to enable another user to access, via a first computer, analyte data obtained from a host-patient associated with a receiver and/or an analyte report for the host-patient associated with the receiver; receiving, in response to the sending, the share code generated by the server, wherein the share code comprises a checksum portion, a password portion, and an identifier portion indicative of the host-patient; generating a user interface view including the share code; and displaying the user interface view including the share code, wherein the share code enables the other user to access, via the first computer, the analyte data and/or the analyte report. Related systems, methods, and articles of manufacture are also disclosed.

Abstract: An electronic device according to various embodiments may include a communication module, and a processor operatively connected to the communication module, wherein the processor is configured to transmit device information of the electronic device to a cloud server or at least one external device located on a local network using the communication module, identify at least one device determined as a provisioning device of an edge computing service from among the electronic device or the at least one external device, receive, based on the electronic device being determined as the provisioning device, authentication information of at least one device, for which the edge computing service is to be provided, from the cloud server the communication module, and perform provisioning related to the edge computing service based on the authentication information.

Abstract: The present invention provides a memory system in which a semiconductor memory device can be accessed properly. The memory system includes a memory controller and a semiconductor memory device. The memory controller sends a command, an address, and first checking data to the semiconductor memory device. When the semiconductor memory device receives first response information that indicates that no error has been detected, it sends or receives read data or write data from the semiconductor memory device. When the semiconductor memory device receives the command, the address, and the first checking data, it uses the first checking data to detect errors in the command and the address, and sends the first reply information when no error is detected, and when no error is detected in the command and the address, it sends or receives read data or write data from the semiconductor memory device.

Abstract: A fuse block unit includes a share flip-flop. The share flip-flop includes a first switch element, a second switch element, a third switch element, a fourth switch element, a first latch, and a second latch. The first switch element selectively couples a first laser latch to a first node according to the first load voltage. The second switch element selectively couples a second laser latch to the first node according to the second load voltage. The third switch element selectively couples an input node to the first node according to the inverted shift voltage. The first latch is coupled between the first node and a second node. The fourth switch element selectively couples the second node to a third node according to the shift voltage. The second latch is coupled between the third node and an output node.

Abstract: The disclosed MTJ read circuits include a current steering element coupled to the read path. At a first node of the current steering element, a proportionally larger current is maintained to meet the requirements of a reliable voltage or current sensing. At a second node of the current steering element, a proportionally smaller current is maintained, which passes through the MTJ structure. The current at the first node is proportional to the current at the second node such that sensing the current at the first node infers the current at the second node, which is affected by the MTJ resistance value.