Abstract: A method for programming a non-volatile memory structure, comprises initiating a two-dimensional fractional number of bits-per-cell programming scheme of a plurality of memory cells, wherein the memory structure comprises: (1) a first memory array comprising a first population of memory cells and the associated peripheral circuitry disposed below the first population of cells, (2) a second memory array positioned above the first memory array and comprising a second population of memory cells and associated peripheral circuitry disposed above the second population of cells, and (3) a data bus tap electrically coupling the first and second memory arrays. Further, the method comprises: (1) storing input data in data latches associated with the first array and with the second array. Additionally, the method comprises converting the stored data using data conversion logic implemented by a data path circuit of the first and second arrays and rewriting the converted data to the latches.

Abstract: A semiconductor apparatus implementing a high speed data output and compensating a resetting of a latch circuit is provided. A readout method of a NAND type flash memory includes: a pre-charging step performing a pre-charging on a bit line and a NAND string connected to the bit line through a sense node (SNS); a resetting step performing a resetting on the latch circuit after the pre-charging; and a discharging step performing a discharging on the NAND string after the resetting.

Abstract: A data processing device may include a processor, configured to combine a first data word and a second data word of a plurality of secret data words by storing, for each of the first data word and the second data word, for an Exclusive-Or sharing of the data word into multiple partial representatives, for at least one of the partial representatives, a transformed version of the partial representative in a processor register, and, if the combination of the data words requires a partial representative of the first data word to be combined with a partial representative of the second data word that is stored in a processor register after having been transformed, combining the partial representative of the first data word with the partial representative of the second data word with a processor operation that takes into consideration that the partial representative of the second data word has been transformed.

Abstract: A memory subsystem and method for performing calibrations therein is disclosed. A memory subsystem includes a memory controller coupled to a memory by a plurality of signal paths. The memory controller is configured to perform an initial calibration to determine respective eye patterns corresponding to the ones of the plurality of signal paths. For a subsequent calibrations, updated eye patterns are determined for a subset of the plurality of signal paths. Remaining ones of the plurality of signal paths (not included in the subset), are not active during the subsequent calibrations. Updated eye patterns for the remaining ones of the plurality of signal paths are determined based on information obtained during the initial calibration and information from signal paths in the subset designated proxies for the remaining ones of the plurality of signal paths.

Abstract: A data processing system includes a memory configured to receive memory access requests. Each memory access request having a corresponding access address and having a corresponding parity bit for an address value of the corresponding access address. The corresponding access address is received over a plurality of address lines and the parity bit is received over a parity line. The memory includes a memory array having a plurality of memory cells arranged in rows, each row having a corresponding word line of a plurality of word lines, and a row decoder coupled to the plurality of address lines, the parity line, and the plurality of word lines. The row decoder is configured to selectively activate a selected word line of the plurality of word lines based on the corresponding access address and the corresponding parity bit of a received memory access request.

Abstract: A method includes detecting proximity between a mobile device and a remote device associated with a transaction reserved by a user of the mobile device and a mode of the electronic device. A verification password is sent to the remote device responsive to detecting the proximity and the mode. A device includes a module to detect proximity between the device and a remote device associated with a transaction reserved by a user of the device occurring within a predefined distance threshold and a processor coupled to the module. A device includes another module to detect a stationary mode of the electronic device occurring for at least a predefined duration threshold. The processor is sends a verification password to the remote device responsive to detecting the proximity and the mode.

Abstract: Various implementations described herein refer to an integrated circuit having a first memory structure and a second memory structure. The first memory structure is disposed in a first area of the integrated circuit, and the first memory structure has first memory cells with first transistors. The second memory structure is disposed in a second area of the integrated circuit that is different than the first area, and the second memory structure has second memory cells with second transistors that are separate from the first transistors. The second transistors of the second memory cells are arranged to provide an output oscillating frequency for detecting variation of performance of the first transistors of the first memory cells.

Abstract: A semiconductor device includes a pre-pulse generation circuit configured to generate a pre-pulse, based on a write shifting pulse and a write leveling activation signal; a write control signal generation circuit configured to generate a write control signal, based on the pre-pulse and a division clock; and a write leveling control circuit configured to generate detection data including information on a phase difference between a data clock and a system clock, based on the pre-pulse and the division clock.

Abstract: Attachments or other documents can be transmitted to a sandbox environment where they can be concurrently opened for remote preview from an endpoint and scanned for possible malware. A gateway or other intermediate network element may enforce this process by replacing attachments, for example, in incoming electronic mail communications, with links to a document preview hosted in the sandbox environment.

Abstract: The present technology relates to a memory device. A memory device according to the present technology may include a plurality of planes, individual operation controllers configured to respectively control read operations on the plurality of planes, a common operation controller configured to control a program operation or an erase operation on any one of the plurality of planes, a command decoder configured to provide a read command among the plurality of commands to an individual operation controller that controls a plane that is indicated by an address that corresponds to the read command among the individual operation controllers, and configured to provide a program command or an erase command among the plurality of commands to the common operation controller, and a peripheral circuit configured to generate operation voltages that are used for the read operations, the program operation, and the erase operation.

Abstract: Methods, systems, and apparatus for quantum random number generation. In one aspect, a method includes initializing N qubits in respective superposition states; computing a randomly selected oracle randomization function using i) the initialized N qubits and ii) multiple ancilla qubits, wherein the multiple ancilla qubits comprise a first ancilla qubit and one or more second ancilla qubits; performing a phase flip operation on the first ancilla qubit; computing an inverse of the randomly selected oracle randomization function using i) the N qubits and ii) the multiple ancilla qubits; performing a diffusion operation on the N qubits; and measuring the N qubits and providing data representing the measured states of the N qubits as N random bits.

Abstract: A memory device includes a printed circuit board having a plurality of conductive layers; memory chips mounted over the printed circuit board, wherein the memory chips comprise at least a first number of memory chips and a second number of memory chips; a first power module mounted over the printed circuit board and for providing a first set of power supplies to the first number of memory chips through the plurality of conductive layers; and a second power module mounted over the printed circuit board and for providing a second set of power supplies to the second number of memory chips through the plurality of conductive layers.

Abstract: Various aspects of triggering and controlling workflows are disclosed, where a workflow processes data across a plurality of services by performing a predefined operation using predefined parameters when triggered by a predefined input. Specifically, the various aspects include providing access control for workflows triggered using button sharing, encoding workflows and scanning encoded workflows to trigger workflows, using security badges and access control systems used at workplaces to trigger workflows, and enabling workflows to extract information from mobile devices and using the information for subsequent processing.

Abstract: A signal processing circuit includes a delay locked loop (DLL) circuit, a data output path circuit, and a first phase detector circuit. The DLL circuit is arranged to receive a memory clock signal, and generate a DLL output signal according to the memory clock signal and a DLL feedback signal. The data output path circuit is coupled to the DLL circuit, and is arranged to generate a DQS signal according to the DLL output signal. The first phase detector circuit is coupled to the data output path circuit, and is arranged to receive the memory clock signal and the DQS signal, and detect a phase difference between the memory clock signal and the DQS signal to generate a first phase detection result.

Abstract: A computerized process is described for transferring content from a first entity to a second entity including first transferring separately and via a database entity for each content: a content identifier, content rights, a content encryption key, a content initialization vector, a content encryption count, and a first entity identifier. Included with the transferred content is a transfer identifier, which is encrypted. After transferred content is received by the second entity, the transfer identifier is used to retrieve the content rights, content encryption key, content encryption initialization vector, content encryption count, and first entity identifier from the database entity. After receiving the content, both actions taken on the content and disposition of the content at the second entity are controlled according to the content rights by the first entity and the status of the content is reported to the first entity via a database entity.

Abstract: Techniques, apparatus, and devices for managing power in a memory die are described. A memory die may include an array of memory cells and one or more voltage sensors. Each voltage sensor may be on the same substrate as the array of memory cells and may sense a voltage at a location associated with the array. The voltage sensors may generate one or more analog voltage signals that may be converted to one or more digital signals on the memory die. In some cases, the analog voltage signals may be converted to digital signals using an oscillator and a counter on the memory die. The digital signal may be provided to a power management integrated circuit (PMIC), which may adjust a voltage supplied to the array based on the digital signal.

Abstract: Word-line drivers, memories, and methods of operating word-line drivers are provided. A word-line driver coupled to an array of memory cells includes a decoder powered by a first power supply. The decoder is configured to decode an address to provide a plurality of word-line signals. The word-line driver also includes a plurality of output stages powered by a second power supply that is different than the first power supply. Each of the output stages includes a first transistor having a gate controlled by a first control signal and an inverter. The inverter is coupled between the first transistor and a ground and has an input coupled to the decoder to receive one of the word-line signals. The word-line driver also includes pull-down circuitry coupled between the gates of the first transistors and the ground and activated by a second control signal.

Abstract: Techniques for searching an inverted index associating byte sequences of a fixed length and files that contain those byte sequences are described herein. Byte sequences comprising a search query are determined and searched in the inverted index. In some examples, training data for training machine learning model(s) may be created using pre-featured data from the inverted index. In various examples, training data may be used to retrain a ML model until the ML model meets a criterion. In some examples, the trained ML model may be used to perform searches on the inverted index and classify files.

Abstract: Methods, systems, and devices for signal sampling with offset calibration are described. For example, sampling circuitry may include an input pair of transistors where input signals may be provided to gate nodes of the transistors, and an output signal may be generated based on a comparison of voltages of drain nodes of the transistors. In some examples, source nodes of the transistors may be coupled with each other, such as via a resistance, and each source node may be configured to be coupled with a ground node. In some examples, a conductive path between the source nodes may be coupled with one or more switching components configurable for further coupling of the source nodes with the ground node. In some examples, enabling such switching components may add an electrical characteristic (e.g., capacitance) to the conductive path between the source nodes, which may be configurable to mitigate sampling circuitry imbalances.

Abstract: An example method of sharing a resource between software containers includes detecting a request from a first software container to access a resource of a different, second software container, an operational state of the second software container being controlled by a container engine running on the host computing device. The method also includes accepting or rejecting the request based on whether the first and second software containers, which each contain a respective software application, are part of a same logical software application. An example host computing device configured to share resources between software containers is also disclosed.