Patents Examined by Mohammad Choudhry
  • Patent number: 10283353
    Abstract: A method of reforming an insulating film deposited on a substrate having a recess pattern constituted by a bottom and sidewalls, includes: providing the film deposited on the substrate having the recess pattern in an evacuatable reaction chamber, wherein a property of a portion of the film deposited on the sidewalls is inferior to that of a portion of the film deposited on a top surface of the substrate; adjusting a pressure of an atmosphere of the reaction chamber to 10 Pa or less, which atmosphere is constituted by H2 and/or He without a precursor and without a reactant; and applying RF power to the atmosphere of the pressure-adjusted reaction chamber to generate a plasma to which the film is exposed, thereby reforming the portion of the film deposited on the sidewalls to improve the property of the sidewall portion of the film.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: May 7, 2019
    Assignee: ASM IP Holding B.V.
    Inventors: Akiko Kobayashi, Masaru Zaitsu, Nobuyoshi Kobayashi, Masaru Hori
  • Patent number: 10269639
    Abstract: Disclosed herein is a method of manufacturing a packaged wafer including a step of forming grooves in a face side of a wafer along projected dicing lines to a depth larger than a finished thickness of the wafer, a step of forming a ring-shaped groove in and along a boundary between a device area and an outer peripheral excess area of the wafer to a depth larger than the depth of the grooves, and a step of placing a recess mold of a molding apparatus in engagement with the wafer so that a side wall of the recess mold is placed on a bottom of the ring-shaped groove and filling a space between the recess mold and the wafer with a molding resin.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: April 23, 2019
    Assignee: Disco Corporation
    Inventors: Hideki Koshimizu, Xin Lu, Yurika Araya
  • Patent number: 10249723
    Abstract: A semiconductor device includes a semiconductor body having a main surface and an active region surrounded by a non-active region. A trench extends from the main surface into the semiconductor body. The trench has a stripe configuration and extends laterally within the active region. A first electrode and a first insulator are in the trench. The first insulator insulates the first electrode from the semiconductor body. The first electrode is recessed in the trench and has a planar surface extending generally parallel with and below the main surface of the semiconductor body so as to define a well in the trench that is laterally confined by the first insulator. A second insulator is on the planar surface. A second electrode is within the well of the trench, and the second insulator insulates the second electrode from the first electrode.
    Type: Grant
    Filed: December 26, 2017
    Date of Patent: April 2, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Heimo Hofer, Martin Poelzl, Maximilian Roesch, Britta Wutte
  • Patent number: 10249441
    Abstract: A process of forming a photoactive layer of a planar perovskite photoactive device comprising: applying at least one layer of a first precursor solution to a substrate to form a first precursor coating on at least one surface of the substrate, the first precursor solution comprising MX2 and AX dissolved in a first coating solvent, wherein the molar ratio of MX2:AX=1:n with 0<n<1; and applying a second precursor solution to the first precursor coating to convert the first precursor coating to a perovskite layer AMX3, the second precursor solution comprising AX dissolved in a second coating solvent, the first precursor solution reacting with the second precursor solution to form a perovskite layer AMX3 on the substrate, wherein A comprises an ammonium group or other nitrogen containing organic cation, M is selected from Pb, Sn, Ge, Ca, Sr, Cd, Cu, Ni, Mn, Co, Zn, Fe, Mg, Ba, Si, Ti, Bi, or In, X is selected from at least one of F, Cl, Br or I.
    Type: Grant
    Filed: January 21, 2016
    Date of Patent: April 2, 2019
    Assignee: COMMONWEALTH SCIENTIFIC AND INDUSTRIAL RESEARCH ORGANISATION
    Inventors: Doojin Vak, Youn-Jung Heo
  • Patent number: 10242911
    Abstract: A semiconductor device includes a first trench on a mandrel line through a top mask layer and stopping at a middle mask layer; and a second trench on a non-mandrel line through the top mask layer and stopping at the middle mask layer. A spacer material is removed from a structure resulting from etching the first trench and the second trench. The device includes a first via structure, formed using a removable material, in the first trench; a second via structure, formed using a removable material, in the second trench; an air-gap formed in a third trench created at a location of the spacer; a fourth trench formed by etching, to remove the first via structure and a first portion of a bottom mask layer under the first via structure; and a self-aligned line-end via on the mandrel line formed by filling the fourth trench with a conductive metal.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: March 26, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lawrence A. Clevenger, Carl J. Radens, John H. Zhang
  • Patent number: 10242866
    Abstract: It will be understood that in some embodiments, nitrogen-containing ligands bonded to the silicon may not necessarily be identical to another nitrogen-containing ligand bonded to the same silicon atom. For example, in some embodiments, R1 and R2 may be different alkyl ligands. In some embodiments, a first NR1R2 ligand attached to a silicon atom may not be the same as or have the same alkyl ligands as another NR1R2 ligand attached to the same silicon atom. As noted above, R1 and R2 may be any alkyl ligand.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: March 26, 2019
    Assignee: Lam Research Corporation
    Inventors: David Charles Smith, Dennis M. Hausmann
  • Patent number: 10236350
    Abstract: At least one method, apparatus and system disclosed herein for forming a finFET device. A gate structure comprising a gate spacer on a semiconductor wafer is formed. A self-aligned contact (SAC) cap is formed over the gate structure. A TS structure is formed. At least one M0 metal structure void is formed. At least one CB structure void adjacent the M0 metal structure void is formed. An etch process is performed the M0 and CB structures voids to the gate structure. At least one CA structure void adjacent the CB structure void is formed. The M0, CB, and CA structure voids are metallized.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: March 19, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Guillaume Bouche, Tuhin Guha Neogi, Sudharshanan Raghunathan, Andy Chi-Hung Wei, Jason Eugene Stephens, Vikrant Kumar Chauhan, David Michael Permana
  • Patent number: 10211763
    Abstract: As speed operation range identification system for motion systems driven by permanent magnet synchronous motors (PMSMs) or induction motors leverages both characteristics of the motor as well as dynamic characteristics of the motion system—including the friction and load—to identify suitable maximum speeds for operation of the motion system in the normal speed and field weakening regions. The identification system can model both motor characteristics as well as real-time dynamics of the controlled mechanical system that may vary during operation. The system can apply an optimization algorithm to this model to determine suitable maximum speeds for operation in the normal speed and/or field weakening regions. The determined maximum speeds can be used to perform substantially real-time adjustments to motion profile limits or current reference values generated by the motor controller in order to ensure that the speed of the system remains below the determined maximum.
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: February 19, 2019
    Assignee: LINESTREAM TECHNOLOGIES
    Inventor: Gang Tian
  • Patent number: 10211300
    Abstract: According to an embodiment of a method of forming a semiconductor device, a semiconductor layer including a first dopant species of a first conductivity type and a second dopant species of a second conductivity type different from the first conductivity type is formed. The semiconductor layer is part of a semiconductor body having opposite first and second surfaces. Trenches are formed in the semiconductor layer at the first surface. The trenches are filled with a filling material including at least a semiconductor material. A thermal oxide is formed at one or both of the first and second surfaces, the thermal oxide having a thickness of at least 200 nm. Thermal processing of the semiconductor body causes diffusion of the first and second dopants species into the filling material.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: February 19, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Franz Hirler, Gabor Mezoesi, Hans Weber
  • Patent number: 10211365
    Abstract: A method for producing optoelectronic devices, including the following successive steps: providing a substrate having a first face; on the first face, forming sets of light-emitting diodes including wire-like, conical or frustoconical semiconductor elements; covering all of the first face with a layer encapsulating the light-emitting diodes; forming a conductive element that is insulated from the substrate and extends through the substrate from the second face to at least the first face; reducing the thickness of the substrate; and cutting the resulting structure in order to separate each set of light-emitting diodes.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: February 19, 2019
    Assignees: Commissariat à l'Énergie Atomique et aux Énergies Alternatives, Aledia
    Inventors: Christophe Bouvier, Emilie Pougeoise, Xavier Hugon, Carlo Cagli, Tiphaine Dupont, Philippe Gibert, Nacer Aitmani
  • Patent number: 10199276
    Abstract: Fabrication of an integrated circuit comprising: at least one first transistor made at least partially in a first semiconducting layer, at least one second transistor made at least partially in a second semiconducting layer formed above the first semiconducting layer, an insulating layer formed between the first transistor and the second transistor, one or several connection elements passing through the insulating layer between the first and the second transistor, at least one connection element being connected to the first and/or the second transistor and being based on a metal-semiconductor alloy.
    Type: Grant
    Filed: October 26, 2016
    Date of Patent: February 5, 2019
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Claire Fenouillet-Beranger, Fabrice Nemouchi
  • Patent number: 10193004
    Abstract: A method for metallization includes providing a transparent donor substrate (34) having deposited thereon a donor film (36) including a metal with a thickness less than 2 pm. The donor substrate is positioned in proximity to an acceptor substrate (22) including a semiconductor material with the donor film facing toward the acceptor substrate and with a gap of at least 0.1 mm between the donor film and the acceptor substrate. A train of laser pulses, having a pulse duration less than 2 ns, is directed to impinge on the donor substrate so as to cause droplets (44) of the metal to be ejected from the donor layer and land on the acceptor substrate, thereby forming a circuit trace (25) in ohmic contact with the semiconductor material.
    Type: Grant
    Filed: October 19, 2015
    Date of Patent: January 29, 2019
    Assignee: ORBOTECH LTD.
    Inventors: Michael Zenou, Zvi Kotler
  • Patent number: 10186424
    Abstract: Compositions for forming thin, silicon-containing antireflective coatings and methods of using these compositions in the manufacture of electronic devices are provided. Silicon-containing antireflective coatings formed from these compositions can be easily removed during processing without the need for a separate removal step.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: January 22, 2019
    Assignee: Rohm and Haas Electronic Materials LLC
    Inventors: Suzanne M. Coley, Paul J. LaBeaume, Shintaro Yamada, Cecilia W. Kiarie, Li Cui, Bhooshan Popere
  • Patent number: 10181459
    Abstract: A method of manufacturing a light-emitting device incudes providing a supporting member having a recess; disposing a light-emitting element at a bottom surface of the recess; disposing a first light-reflecting resin at the bottom surface of the recess; disposing a second light-reflecting resin in the recess, a viscosity of the second light-reflecting resin being higher than a viscosity of the first light-reflecting resin; and curing the first light-reflecting resin and the second light-reflecting resin to form a light-reflecting wall.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: January 15, 2019
    Assignee: NICHIA CORPORATION
    Inventors: Kenji Ozeki, Takakazu Kono, Kunihito Sugimoto
  • Patent number: 10170699
    Abstract: The present disclosure relates to a method of forming a resistive random access memory (RRAM) cell having a reduced leakage current, and an associated apparatus. In some embodiments, the method is performed by forming a bottom electrode layer over a lower metal interconnect layer. A dielectric data storage layer having a variable resistance is formed onto the bottom electrode layer in-situ with forming at least a part of the bottom electrode layer. A top electrode layer is formed over the dielectric data storage layer. By forming the dielectric data storage layer in-situ with forming at least a part of the bottom electrode layer, leakage current, leakage current distribution and device yield of the RRAM cell are improved.
    Type: Grant
    Filed: February 15, 2017
    Date of Patent: January 1, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Trinh Hai Dang, Hsing-Lien Lin, Kai-Wen Cheng, Cheng-Yuan Tsai, Chia-Shiung Tsai, Ru-Liang Lee
  • Patent number: 10168477
    Abstract: According to an aspect of the present principles, methods are provided for fabricating an integrated structure. A method includes forming a very large scale integration (VLSI) structure including a semiconductor layer at a top of the VLSI structure. The method further includes mounting the VLSI structure to a support structure. The method additionally includes removing at least a portion of the semiconductor layer from the VLSI structure. The method also includes attaching an upper layer to the top of the VLSI structure. The upper layer is primarily composed of a material that has at least one of a higher resistivity or a higher transparency than the semiconductor layer. The upper layer includes at least one hole for at least one of a photonic device or an electronic device. The method further includes releasing said VLSI structure from the support structure.
    Type: Grant
    Filed: November 17, 2016
    Date of Patent: January 1, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Aydin Babakhani, Steven A. Cordes, Jean-Olivier Plouchart, Scott K. Reynolds, Peter J. Sorce, Robert E. Trzcinski
  • Patent number: 10168478
    Abstract: According to an aspect of the present principles, methods are provided for fabricating an integrated structure. A method includes forming a very large scale integration (VLSI) structure including a semiconductor layer at a top of the VLSI structure. The method further includes mounting the VLSI structure to a support structure. The method additionally includes removing at least a portion of the semiconductor layer from the VLSI structure. The method also includes attaching an upper layer to the top of the VLSI structure. The upper layer is primarily composed of a material that has at least one of a higher resistivity or a higher transparency than the semiconductor layer. The upper layer includes at least one hole for at least one of a photonic device or an electronic device. The method further includes releasing said VLSI structure from the support structure.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: January 1, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Aydin Babakhani, Steven A. Cordes, Jean-Olivier Plouchart, Scott K. Reynolds, Peter J. Sorce, Robert E. Trzcinski
  • Patent number: 10153761
    Abstract: A half bridge circuit includes a sapphire substrate, a GaN upper switch on the sapphire substrate, a GaN lower switch on the sapphire substrate and coupled to the GaN upper switch, a first conductor coupled to the upper switch, a second conductor coupled to the lower switch, and a capacitor. A portion of the first conductor and a portion of the second conductor are on a plane vertically separated from the upper switch and the lower switch by a height, and the capacitor is coupled between the portion of the first conductor and the portion of the second conductor.
    Type: Grant
    Filed: February 26, 2016
    Date of Patent: December 11, 2018
    Assignee: HRL Laboratories, LLC
    Inventors: Brian Hughes, Rongming Chu
  • Patent number: 10147800
    Abstract: A method of fabricating a transistor with reduced hot carrier injection effects includes providing a substrate covered by a gate material layer. Later, the gate material layer is patterned into a gate electrode. Then, a mask layer is formed to cover part of the gate electrode and expose two ends of the gate electrode. Finally, a first implantation process is performed to implant dopants through the exposed two ends of the gate electrode into the substrate directly under the gate electrode to form two LDD regions by taking the mask layer as a mask.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: December 4, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kuan-Liang Liu, Shih-Yin Hsiao, Ching-Chung Yang
  • Patent number: 10134804
    Abstract: A method of forming a light-emitting device. The light-emitting device includes a first optoelectronic unit, a second optoelectronic unit, a fence, and a cover. The first optoelectronic unit has a first side surface. The second optoelectronic unit is apart from the first optoelectronic unit and has a second side surface. The fence surrounds the first side surface and the second side surface. The cover is on the first optoelectronic unit and the fence.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: November 20, 2018
    Assignee: Epistar Corporation
    Inventors: Min Hsun Hsieh, Hsin-Mao Liu