Abstract: A divider which divides a wafer having a division start points formed along the scheduled divisions into a plurality of device chips. The divider includes a placement table on which a wafer is placed, and division unit adapted to divide the wafer on the placement table into a plurality of device chips starting from the division start points. The placement table includes: a plurality of spherical bodies having the same diameter; a container that accommodates the plurality of spherical bodies in close contact with each other; and a placement surface formed by connecting vertices of spherical surfaces of the plurality of spherical bodies that are accommodated in close contact with each other.

Abstract: Apparatus, systems, and methods are provided to generate markings on the surface of a die or substrate. The markings represent information. The markings can be annealed onto the surface of the die or substrate using a laser. Another embodiment can use an out-of-focus laser beam to mark a solder resist material.

Abstract: To reduce defects in an oxide semiconductor film in a semiconductor device. To improve electrical characteristics of and reliability in the semiconductor device including an oxide semiconductor film. A method for manufacturing a semiconductor device includes the steps of forming a gate electrode and a gate insulating film over a substrate, forming an oxide semiconductor film over the gate insulating film, forming a pair of electrodes over the oxide semiconductor film, forming a first oxide insulating film over the oxide semiconductor film and the pair of electrodes by a plasma CVD method in which a film formation temperature is 280° C. or higher and 400° C. or lower, forming a second oxide insulating film over the first oxide insulating film, and performing heat treatment at a temperature of 150° C. to 400° C. inclusive, preferably 300° C. to 400° C. inclusive, further preferably 320° C. to 370° C. inclusive.

Abstract: A manufacturing method of a two-dimensional transition-metal chalcogenide thin film includes providing a substrate, providing a reaction film, providing a source and providing a microwave. The substrate is made of material having dipole moments. The reaction film, disposed on the substrate, has a predefined thickness and includes a transition-metal compound. The source includes S, Se, or Te. The substrate is heated by the microwave to produce a heat energy to the reaction film and the source; thus a chemical reaction takes place and the two-dimensional transition-metal chalcogenide thin film is formed on the substrate. The two-dimensional transition-metal thin film includes a plurality of elements, and each of the elements aligns along a predefined direction by controlling a value of the predefined thickness.

Abstract: A process for constructing a superconducting Josephson-based nonvolatile quantum memory device comprising: sequentially depositing on a silicon substrate a thermal oxide buffer layer, a superconductor bottom-electrode thin film, and an oxide isolation layer; patterning an active window having dimensions smaller that 10 nanometers in the oxide isolation layer; then sequentially depositing a bottom tunnel oxide layer, a charge-trapping layer, a top cap, and a top superconductor electrode layer; defining an active region by dry etching down to the oxide isolation layer while protecting the active region from etch chemistry; depositing a device passivation layer; defining and patterning vias from a top of the device passivation layer to the superconductor bottom-electrode thin film and to the top superconductor electrode of the active region; and depositing metal interconnect into the vias.

Abstract: An embodiment of a semiconductor memory device including a multi-layer charge storing layer and methods of forming the same are described. Generally, the device includes a channel formed from a semiconducting material overlying a surface on a substrate connecting a source and a drain of the memory device; a tunnel oxide layer overlying the channel; and a multi-layer charge storing layer including an oxygen-rich, first oxynitride layer on the tunnel oxide layer in which a stoichiometric composition of the first oxynitride layer results in it being substantially trap free, and an oxygen-lean, second oxynitride layer on the first oxynitride layer in which a stoichiometric composition of the second oxynitride layer results in it being trap dense. In one embodiment, the device comprises a non-planar transistor including a gate having multiple surfaces abutting the channel, and the gate comprises the tunnel oxide layer and the multi-layer charge storing layer.

Abstract: A heated non-contact wafer handling gripper may heat a thin device wafer bottom surface having a temporary bonding adhesive residue after debonding of the device wafer from a carrier along a layer of temporary bonding adhesive that bonds the wafers. The gripper may heat residue of the adhesive that remains on the bottom surface while gripping, transferring and placing the wafer onto an adhesive cleaning chuck. The heated adhesive cleaning chuck may heat the thin device wafer bottom surface having the adhesive residue after being placed on the chucks. The chuck may heat the residue of the adhesive while the residue is cleaned from the wafer. Due to the heating by the chuck and/or gripper, wafer warpage and associated problems due to cooling of the residue may be eliminated or acceptable for wafer handling and adhesive cleaning.

Abstract: Disclosed is a light emitting device package including a package body including at least one electrode pad disposed on a surface thereof, a light emitting device disposed on the package body, the light emitting device being electrically connected to the electrode pad through a wire, and a via hole electrode passing through the package body, wherein the wire forms a stitch on at least one of the light emitting device and the electrode pad, the light emitting device package further includes a bonding ball disposed on the stitch, and the via hole electrode non-overlaps the stitch and the bonding ball in a vertical direction.

Abstract: Some embodiments include methods of forming semiconductor constructions. Alternating layers of n-type doped material and p-type doped material may be formed. The alternating layers may be patterned into a plurality of vertical columns that are spaced from one another by openings. The openings may be lined with tunnel dielectric, charge-storage material and blocking dielectric. Alternating layers of insulative material and conductive control gate material may be formed within the lined openings. Some embodiments include methods of forming NAND unit cells. Columns of alternating n-type material and p-type material may be formed. The columns may be lined with a layer of tunnel dielectric, a layer of charge-storage material, and a layer of blocking dielectric. Alternating layers of insulative material and conductive control gate material may be formed between the lined columns. Some embodiments include semiconductor constructions, and some embodiments include NAND unit cells.

Abstract: Various methods include: forming an opening in a resist layer to expose a portion of an underlying blocking layer; performing an etch on the exposed portion of the blocking layer to expose a portion of an etch stop layer, wherein the etch stop layer resists etching during the etch of the exposed portion of the blocking layer; etching the exposed portion of the etch stop layer to expose a portion of a substrate below the exposed portion of the etch stop layer and leave a remaining portion of the etch stop layer; and ion implanting the exposed portion of the substrate, wherein the blocking layer prevents ion implanting of the substrate outside of the exposed portion.

Abstract: Embodiments provided herein describe methods for forming cadmium-manganese-telluride (CMT), such as for use in photovoltaic devices. A substrate including a material with a zinc blend crystalline structure is provided. CMT is formed above the substrate. During the formation of the CMT, cation-rich processing conditions are maintained. The resulting CMT may be more readily provided with p-type dopants when compared to conventionally-formed CMT.

Abstract: Provided are methods for processing semiconductor substrates or, more specifically, etching silicon containing antireflective coatings (SiARCs) from the substrates while preserving silicon oxides layers disposed on the same substrates. An etching solution including sulfuric acid and hydrofluoric acid may be used for these purposes. In some embodiments, the weight ratio of sulfuric acid to hydrofluoric acid in the etching solution is between about 15:1 and 100:1 (e.g., about 60:1). The temperature of the etching solution may be between about 30° C. and 50° C. (e.g., about 40° C., during etching). It has been found that such processing conditions provide a SiARC etching rate of at least about 50 nanometers per minute and selectivity of SiARC over silicon oxide of greater than about 10:1 or even greater than about 50:1. The same etching solution may be also used to remove photoresist, organic dielectric, and titanium nitride.

Abstract: The present invention provides an image sensor device including a substrate, a channel formed in the substrate, a photoelectric transfer region formed in the substrate located at one side of the channel, a voltage transfer region formed in the substrate located at the other side of the channel, a first gate dielectric layer formed on the substrate, a second gate dielectric layer formed on the substrate, wherein the first gate dielectric layer and the second gate dielectric layer have a joint above the channel, and the thickness of the first gate dielectric layer is thicker than that of the second gate dielectric layer, and a gate formed on the first gate dielectric layer and the second gate a is dielectric layer. The present invention also provides a method for fabricating the image sensor device.

Abstract: A fingerprint sensor package, including a sensing side for sensing fingerprint information and a separate connection side for electrically connecting the fingerprint sensor package to a host device, is disclosed. The fingerprint sensor package can also include a sensor integrated circuit facing the sensing side and substantially surrounded by a fill material. The fill material includes vias at peripheral locations around the sensor integrated circuit. The fingerprint sensor package can further include a redistribution layer on the sensing side which redistributes connections of the sensor integrated circuit to the vias. The connections can further be directed through the vias to a ball grid array on the connection side. Some aspects also include electrostatic discharge traces positioned at least partially around a perimeter of the connection side. Methods of manufacturing are also disclosed.

Abstract: Oxide growth of a gate dielectric layer that occurs between processes used in the fabrication of a gate dielectric structure can be reduced. The reduction in oxide growth can be achieved by maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth of the gate dielectric layer between at least two sequential process steps used in the fabrication the gate dielectric structure. Maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth also improves the uniformity of nitrogen implanted in the gate dielectric.

Abstract: Systems and methods for reducing copper contamination in a substrate processing system include performing a plasma process on a substrate in a processing chamber of a substrate processing system. A component is located in the processing chamber and is made of an alloy including copper. The plasma process uses a process gas mixture including molecular hydrogen. Prior to performing the plasma process on the substrate and before the substrate is arranged in the processing chamber, the component is conditioned in the processing chamber using a conditioning plasma process that includes a process gas mixture including molecular oxygen and forming gas.

Abstract: A junction type field effect transistor (JFET) in a substrate includes channel and source regions of a first conductivity type and first through fourth gate regions of a second conductivity type. The first and second gate regions are disposed in a direction along a surface of the substrate. The third and fourth gate regions are disposed in the direction. The first and third gate regions are disposed in a depth direction. The first gate region is disposed between the surface and the third gate region. The second and fourth gate regions are disposed in the depth direction. The second gate region is disposed between the surface and the fourth gate region. The channel region includes a first region disposed between the first and third gate regions and a second region disposed between the second and fourth gate regions. The source region is disposed between the first and second gate regions.

Abstract: A semiconductor light-emitting device includes a light-emitting structure that includes a first conductive semiconductor layer, an active layer, a second conductive semiconductor layer, an electrode layer contacting one of the first conductive semiconductor layer and the second conductive semiconductor layer, and a bonding conductive layer connected to the electrode layer. The bonding conductive layer includes a main bonding layer having a recess area defined by a stepped portion on a surface opposite to a surface facing the electrode layer, and a filling bonding layer filling at least a part of the recess area.

Abstract: A packaging method for an OLED device, including: opening at least one through hole in a cover plate in a region between the region for forming glass cement and the region for applying UV glue; regulating the pressure in a cell-assembling chamber to a first pressure, and cell-assembling a back plate with the cover plate placed on a base board in the cell-assembling chamber with the first pressure lower than the atmospheric pressure; regulating the pressure in the cell-assembling chamber to the atmospheric pressure; curing the UV glue; regulating the pressure in the cell-assembling chamber to a second pressure that is lower than the atmospheric pressure and higher than the first pressure and detaching the cover plate from the base board; and sealing the through hole in the cover plate; and sintering the glass cement.

Abstract: A process for fabricating a field-effect transistor device (20) implemented on a network of vertical nanowires (24), includes: producing a source electrode (26) and a drain electrode (30) at each end of each nanowire (24) symmetrically relative to the gate electrode of each elementary transistor implemented on a nanowire; creating a gate electrode by depositing a layer (38) of conductive material around a layer (36) of dielectric material that surrounds a portion of each nanowire (24), a single conductive layer (38) being used for all of the nanowires and the thickness of the conductive layer corresponding to the gate length of the transistor device; and insulating each electrode with a planar layer (32, 34) of a dielectric material in order to form a nanoscale gate and in order to insulate the contacts of each elementary transistor between the gate and the source and the gate and the drain.