Abstract: A method and apparatus for advantageously utilizing the reset state of an RTZ shift register to guarantee proper data alignment at the feedback taps to facilitate decision feedback equalization (DFE) in a unified signaling system. An input data stream is sliced into an even data stream and an odd data stream, whereby the sliced data is compared to a programmable threshold depending upon a detection mode. Each bit of the even data stream is propagated through RTZ latches and each bit of the odd data stream is propagated through RTZ latches. At any given instant in time, a correct portion of the RTZ latch outputs contain zero information, so that each latch output may be summed in a current mode without the need for any intervening logic. The input data stream is summed in current mode with the feedback data and converted to voltage prior to sampling the currently received data bit.

Abstract: This invention provides a coding method and apparatus capable of increasing the coding efficiency. According to this invention, an image processing apparatus which performs predictive coding using image data of a different frame as a reference picture includes a prediction unit which performs motion compensated prediction for each reference picture in at least one reference list formed from a set of reference pictures for prediction, a reference list update unit which updates the reference list by adding or deleting the reference picture, a reference counter unit which measures, for each reference picture, a count at which the reference picture is used for motion compensation predictive coding, and an update picture determination unit which determines a reference picture to be updated in the reference list by using the measurement result of the reference counter unit.

Abstract: An error tracking apparatus and method for tracking a residual frequency error, a phase error, a timing error, and a signal amplitude variation to enhance a phase error tracking performance and a tracking speed in an orthogonal frequency division multiplexing (OFDM) system is provided.

Abstract: A method is disclosed, including identifying a preamble in a frame, where the preamble has a preamble length 1. M data items received in succession are stored. The m data items once divided into n portions, where the data items in each portion have respectively been received at successive times and where m and n are natural numbers and the following applies to m and n: m>n, m>1, n>1. The n portions are respectively correlated to the expected values to form component correlation results. Delaying the component correlation results, with at least two component correlation results being delayed by different lengths. The method also includes combining the delayed component correlation results to form a total correlation value. The total correlation value is used to determine whether the m received data items contain the preamble of a frame.

Abstract: In a distortion generation path of a power series predistorter, a frequency characteristic compensator that adjusts the frequency characteristic of a distortion component is provided in series with an odd-order distortion generator. The output of a power amplifier is divided to obtain an output signal of the power amplifier, the output signal of the power amplifier is down-converted by a down converter, and a distortion detector detects a distortion component in the down-converted signal of base band. The frequency characteristic of the distortion component is split into windows each having a band width of ?f by a distortion component frequency characteristic splitter, and the power of the distortion component in each window is detected. Based on the detected power, the frequency characteristic compensator adjusts a part of the frequency characteristic of the distortion component associated with each window.

Abstract: The invention is related to a synchronization method in a communication system. The invention includes: carrying out a coarse time offset and frequency offset estimation, first estimating errors in the coarse time-offset and frequency offset estimation by using a maximum-likelihood time-offset estimation and joint optimisation of time-offset and frequency-offset, second estimating frequency offset and time offset by using error estimates in a closed tracking loop.

Abstract: Systems and method to compress digital video based on human factors expressed as a desirability score are provided. A particular method includes passing a digital input signal through a pulse-width modulator and passing an output of the pulse-width modulator through a power switching device. An output of the power switching device has a plurality of pulses. The method includes receiving the output of the power switching device at a first input of a comparator and receiving a reference voltage at a second input of the comparator. The method includes determining a net signal based on an output of the comparator and determining a timing error signal based on the net signal and the digital input signal. The method also includes adjusting the digital input signal to compensate for harmonic distortion based at least in part on the timing error signal.

Abstract: A demodulator for use in a receiver converts a digital baseband signal into inbound digital symbols with reduced hardware complexity and reduced power consumption. The demodulator includes a lowpass filter operably coupled to filter the digital baseband signal to produce a filtered digital baseband signal, and an equalizer operating at a first sampling rate to equalize the frequency response of the digital baseband signal such that the receiver overall in-band frequency response approximates the frequency response of a square root raised cosine filter to produce an adjusted digital baseband signal. An interpolator receives the adjusted digital baseband signal at the first sampling rate and interpolates the adjusted digital baseband signal to produce an interpolated digital baseband signal at a second sampling rate, from which the inbound digital symbols can be generated.

Abstract: The present invention provides a method and apparatus for correcting direct current (DC) offsets in radio output signals. The invention comprises a radio processor and a baseband processor. During a calibration routine, the baseband processor measures DC offset produced by the radio processor, generates a corresponding DC offset correction value, and writes the correction value to a discrete memory in the radio processor via a serial processor interface. During a subsequent normal receive operation, the radio processor reads the DC offset correction value from memory and feeds it into a into a digital to analog converter to produce an analog signal that in turn is fed into a radio receive path to nullify undesired DC offset.

Abstract: According to a method for generating a system time clock in a receiving device for digital packetized elementary data streams (E), the packetized elementary data streams (E) being generated in a transmitting device by sampling at a sampling frequency (fsample) synchronized by a system time clock of the transmitting device, the sampling frequency (fsample) of one data stream is determined in the receiving device, and the program clock reference counter is synchronized with the data stream's sampling frequency.

Abstract: When a receiver (200) receives a signal transmitted from a transmitter, an A/D converter (204) converts the signal into a digital signal having two or more levels by A/D conversion. A zero-level detector (207) converts the signal into a two-level digital signal of positive and negative levels. The converted signals are subjected to spectrum despreading by correlators (206, 208), respectively. Whichever signal has a higher intensity is selected by absolute value detectors (209, 210), a comparator (211), and a switch (212). A decoder (213) decodes the selected signal. In a receiving state where the zero-level detector (207) is selected, the transmitter transmits the transmission signal after the signal is converted into a two-level signal. In a receiving state where the A/D converter (204) is selected, the transmitter transmits the transmission signal after the signal is converted into a signal having two or more levels.

Abstract: An m-code GPS receiver receives m-code GPS communication signals having a multimodal autocorrelation, using an m-code mode identifier unambiguously determining a mode value of one of the m-code modal peaks coherently aligned to a coherent unimodal detected envelope, based on sequential probability estimation in an m-code envelope tracking filter using filter residual estimation or with a coherent m-code and c/a-code tracking filter also based on filter residual estimation, for generating m-code phase errors, for unambiguous and precise m-code code phase tracking in closed feedback loops, for preferred use in navigation systems.

Abstract: A receiver circuit controls a power source of a front-end circuit and a demodulator using a first power source control signal. Upon receiving data of a plurality of receiving slots having a guard bit provided between receiving slots adjacent to each other, the first power source control signal becomes a power source ON signal before starting receiving of the data, then becomes a power source OFF signal within the guard bit, and becomes a power source OFF signal after completing the receiving of the data. The receiver circuit controls a power source of an active filter circuit using a second power source control signal, which becomes a power source OFF signal after completing the receiving of the data after becoming a power source ON signal before starting the receiving of the data.

Abstract: A receiver (1000) includes a direct digital frequency synthesizer (DDFS) (700) and first (1040) and second (1042) mixers. The DDFS (700) has a first output for providing a first local oscillator signal, and a second output for providing a second local oscillator signal offset from a quadrature relationship with the first local oscillator signal by a phase offset. The first mixer (1040) has a first input for receiving a radio frequency (RF) signal, a second input for receiving the first local oscillator signal, and an output for providing an in-phase signal at another frequency. The second mixer (1042) has a first input for receiving the RF signal, a second input for receiving the second local oscillator signal, and an output for providing a quadrature signal at the other frequency. The DDFS (700) may be implemented using first (702) and second (704) memories storing portions of a sinusoidal waveform and extra memories (706, 708) supporting the phase offset.

Abstract: A Radio Frequency (RF) receiver includes a RF front end and a baseband processing module coupled to the RF front end that is operable to receive a time domain signal that includes desired signal and interfering signal time domain training symbols and time domain data symbols.

Abstract: A system for processing radio frequency (RF) signals includes a searcher and a Cluster Path Processor (CPP). The searcher detects a maximum signal energy level and position of at least one of a plurality of individual distinct path signals in a signal cluster, wherein at least a portion of the plurality of individual distinct path signals is received within a duration of a corresponding delay spread. The CPP includes a group finger array having a plurality of group fingers and determines a coarse sampling position of the group finger array based upon the position of the at least one of a plurality of individual distinct path signals in the signal cluster. The CPP determines a fine sampling position based upon determines a composite channel energy estimate for the plurality of individual distinct path signals. Using this fine sampling position, the CPP receives at least a portion of the plurality of individual distinct path signals by the group finger array.

Abstract: A device and a method for processing high data rate serial data includes circuitry for recovering a clock based on the high data rate input data stream and for providing the recovered clock to a circuit portion, for example, a portion of a field programmable gate array fabric, to enable the circuit portion to use either a reference clock or the recovered clock for subsequent processing. The invention specifically allows for different circuitry portions to utilize different clocks, including different recovered clocks, for corresponding functions that are being performed. Applications for the present invention are many but include multi-gigabit transceiver, switching devices, and protocol translation devices. More generally, the device and method provide for application specific clock references to be utilized in order to minimize or eliminate timing mismatch in serial data processing.

Abstract: A channel equalizer includes a first transformer, an estimator, an average calculator, a second transformer, a coefficient calculator, a compensator, and a third transformer. The first transformer converts normal data into frequency domain data, where a known data sequence is periodically repeated in the normal data. The estimator estimates channel impulse responses (CIR) during known data intervals adjacent to each normal data block. The average calculator calculates an average value of the CIRs. The second transformer converts the average value into frequency domain data. The coefficient calculator calculates equalization coefficients using the average value, and the compensator compensates channel distortion of each normal data block using the coefficients. The third transformer converts the compensated data block into time domain data.

Abstract: A system comprises a correlation module that receives modulated signals from R antennas, that correlates each of the modulated signals with Y preamble sequences, and that generates Y correlation values for each of the R antennas, where R and Y are integers greater than or equal to 1. A control module generates correlation sums by adding each of the Y correlation values for one of the R antennas to corresponding ones of the Y correlation values for others of the R antennas, that selects a largest correlation sum from the correlation sums, and that detects one of the preamble sequences in the modulated signals when a magnitude of the largest correlation sum is greater than or equal to a first predetermined threshold.

Abstract: Low power decision feedback equalization (DFE) through applying DFE data to input data in a data latch is disclosed. In one embodiment, a decision feedback equalization (DFE) system to remove a post cursor intersymbol interference (ISI) through feeding back previous data scaled with adaptive weights to the DFE system, with each slice of the DFE system may include a first set of decision feedback digital to analog converters (DACs) to generate a first DFE data obtained through the feeding back the previous data scaled with the adaptive weights and a first data latch to generate an output data of the each slice through applying the first DFE data to an input data of the each slice in the first data latch to remove a first delay caused by performing the applying the first DFE data to the input data of the each slice outside of the first data latch.