Abstract: A system and method for providing a peak power reduced OFDM communications signal are disclosed. The system and method provide peak reduction processing in the time domain followed by inter-symbol interference (ISI) control processing in the frequency domain to maintain modulation errors introduced by the peak reduction processing to an acceptable level. The processing is preferably done on a parallel signal path and the peak corrections with ISI control are added into the main signal path to provide the peak reduced OFDM signal.

Abstract: A system having a signal processor for detection of a signal type of a signal is disclosed. One embodiment includes a processor designed to determine a first variable which is characteristic of a first spectrum element of the signal spectrum, and to determine a second variable which is characteristic of a second spectrum element of the signal spectrum. A system is provided for determination of a ratio between the first variable and the second variable, and a detector which is designed to detect the signal type on the basis of the ratio.

Abstract: The method is for receiving an OFDM signal according to which, during a frequency translation phase, there is introduced a phase and gain imbalance between the phase and quadrature components thereof, and a frequency offset relative to a main carrier of the OFDM signal. The method involves a compensation of the effects of the imbalance even in the presence of the frequency offset and provides a reference signal indicative of the effect of the imbalance and according to which a process is carried out to reduce the effect of the imbalance itself.

Abstract: A reconfigurable multi-code correlation unit for correlating a sequence of chip samples comprising 1) a memory for storing the chip samples; 2) a plurality of add-subtract cells, each add-subtract cell receiving a plurality of real bits, a, and a plurality of imaginary bits, b, from a first chip sample and storing each real bit, a, and each imaginary bit, b, in a data store; and 3) a plurality of sign select units. Each sign select units receives from one add-subtract cell a plurality of first inputs equal to a sum (a+b) of the real bits, a, and the imaginary bits, b, and a plurality of second inputs equal to a difference (a?b) of the real bits, a, and the imaginary bits, b. Each sign select unit generates a plurality of real outputs and a plurality of imaginary outputs, wherein each of the real and imaginary outputs is equal to one of 1) the sum (a+b) multiplied by one of +1 and ?1 and 2) the difference (a?b) multiplied by one of +1 and ?1.

Abstract: A system (101) for clock signal synchronization includes a data analyzer (104) and a synchronized clock signal generator (105) coupled to an RC oscillator (103). The data analyzer (104) generates a digital control signal representing the number of cycles of a reference signal of the RC oscillator (103) during an eight-bit period of an incoming token packet. The synchronized signal clock generator (105) uses the digital control signal to lock a clock signal to packets that have the same bit rate as the token packet.

Abstract: An efficient method and system for detecting frame slip in an inband signalling block in pulse code modulation. The effect of frame slip on the inband signalling block is that the bits following the frame slip are transferred from the signalling block into an adjacent block. The octet slip is detected by searching an error bit in a signalling block by comparing it to a sample block. If an error bit is found, an error count for the adjacent block starting from the error bit is calculated. If the error count is more than one, a second error bit of the signalling block is searched (26) and bits of the adjacent block after second error bit are verified (27). If bits of the adjacent block after the second error bit are not correct, the octet slip cannot be assumed (29). Otherwise the octet slip can be assumed by analyzing error count and error bits.

Abstract: A signal processing apparatus has a plurality of baseline wander correcting units, provided in a processing path in which a predetermined processing is performed on an input signal. At least one of the plurality of baseline wander correcting units includes a correction permission control unit that controls permission or rejection of correction, and baseline wander in the input signal is corrected sequentially by each of the plurality of baseline wander correcting units, based on a control of the correction permission control unit. The baseline wander correcting unit corrects the baseline wander by determining whether or not the baseline correction is to be effected or not, so that the wander of baseline can be efficiently corrected.

Abstract: The present invention provides an elevation based adaptive scheme for setting power threshold in the acquisition of navigational satellite signals. In an embodiment, the elevation based adaptive scheme uses a different series of power thresholds to acquire signals from satellites at different elevation angles instead of using one threshold for all satellites, as is done in the prior art. This scheme exploits the fact that the received signal power level depends on the elevation angle of the satellite at the receiver. This scheme also takes into account the antenna gain variation without having to measure the antenna gain variation.

Abstract: A phase calculation apparatus using a binary search is provided. The phase calculation apparatus includes a quarter surface preprocessor determining the bigger one between an absolute value of I component data and an absolute value of Q component data as horizontal component data and the smaller one as perpendicular component data, and detecting information on a phase region indicating an mth (m=1 to 8) phase region (the mth phase region is between (m?1) ?/4 and m ?/4 in which the I/Q component data are located; a phase representative value detector detecting phase representative values x corresponding to the horizontal component data and the perpendicular component data; and a quarter surface postprocessor calculating phase values of the I/Q component data based on the detected information about the phase region and the detected phase representative values x. The phase can be calculated using a limited memory, low complexity of calculation and regardless of the number of bits of I/Q component data.

Abstract: A receiving circuit which receives information using a multi-carrier signal comprises a phase rotation amount calculator which calculates a phase rotation amount of a multi-carrier signal included in a first frequency band according to a pilot-sub carrier included in the first frequency band, a converter which calculates a phase rotation amount of a multi-carrier signal included in a second frequency band according to the phase rotation amount of the multi carrier signal included in the first frequency band.

Abstract: A system for performing adaptative multi-carrier code division multiple access (AMC-CDMA) includes first circuitry and modulator circuitry. The first circuitry determines a channel performance metric for each of a plurality of channels. The first circuitry determines at least one parameter of bit loading for each of the channels based on the channel performance metric. The modulator circuitry modulates AMC-CDMA signals using the parameters for bit loading in each of the channels for transmission over a wired connection.

Abstract: Disclosed are hybrid heterodyne transmitters and receivers for use in communications systems, or other systems, and the corresponding methods for hybrid heterodyne transmitting and receiving. A heterodyne receiver for converting a continuous time modulated signal to a discrete time digital baseband signal includes a sigma-delta modulator. The sigma-delta modulator is a sigma-delta analog-to-digital converter constructed and arranged to receive a modulated signal at an RF carrier frequency and provide a quantized output at a first intermediate frequency. The heterodyne receiver may also include a digital mixer constructed and arranged to receive a data stream quantized by the sigma-delta analog-to-digital converter and receive a signal at a second mixing frequency. The digital mixer then provides digital signals representative of a baseband signal suitable for digital signal processing.

Abstract: An object of the present invention is to reduce jitter dependent on data patterns by an interface receiver. Another object of the present invention is to provide an LSI capable of automatically adjusting a delay time for jitter reduction so as to be able to control its setting for each device. Since the jitter dependent on the data patterns can be expected according to how the previous state is being placed, the state of data received by the receiver is held, and the timing provided to fetch input data is adjusted according to the held state and the input data. As a control mechanism lying in the receiver, for determining a delay time dependent on the form of mounting, a driver transmits and receives pulse data set at one-cycle intervals and pulse data set at two-cycle intervals as test patterns. The receiver has an automatic control mechanism for determining a delay time optimal to a system from the difference between a rising time of each of pulses different in pulse width and its falling time.

Abstract: A correlator (30) for performing a correlation with a received spread spectrum signal, comprising at least an input (30.1) for inputting samples of a received signal; at least one reference code input (30.2) for inputting at least one reference code, a correlator block comprising a data shift register (36) for receiving the signal samples; a number of register groups (31) comprising a code shift register (33) for receiving at least a part of at least one reference code; and a code register (34) for receiving data from the code shift register (33); configuration pathways (201, 202, 203) for arranging the connections between the code shift register and code register (33, 34) of the register groups (31) in a reconfigurable manner.

Abstract: A direct determination equalizer system (“DDES”) for compensating for the deterministic effects of a transmission channel and a data source is disclosed. The DDES may include an equalizer having equalizer-tap coefficients, a cross-correlator configured to receive the first sampled signal and an ideal signal and in response produce a cross-correlated signal, and a processor in signal communication with the equalizer and the cross-correlator. The equalizer is configured to receive a first sampled signal and in response produce an equalized output data signal sequence and the processor is configured to determine the equalizer-tap coefficients from the cross-correlated signal.

Abstract: A parametric form of G-Rake and chip equalization for closed-loop transmit diversity is provided, that accounts for impairment correlation between transmit antennas. In a closed-loop transmit diversity system, the base station transmits a signal from two or more antennas, using one of a predetermined set of relative phase offsets at one of the antennas. The parametric estimation of the impairment or data covariance is performed by summing terms, including a term for each possible phase offset. The terms are weighted by fitting parameters. The fitting parameters are jointly solved by fitting the impairment or data covariance estimate to a measured impairment or data covariance. In another aspect, a measured impairment covariance is formed by exploiting a special relationship between the pilot channels of the different transmit antennas.

Abstract: A technique for enhanced reconditioning equalizer filter chain for multi-carrier signals is described. The input to a transmitter chain is modified by an enhanced reconditioning equalizer filter chain, prior to being applied to the transmitter. The enhanced reconditioning equalizer filter chain modifies and smoothen the amplitude of the signal. The modified and smoothen signal has its picks reduced which results to lower Crest Factor. The input to the enhanced reconditioning equalizer filter chain could be a baseband, an intermediate frequency (IF) or radio frequency (RF) signal. When the signal is an IF or RF signal it needs to be down converted to baseband before applied to enhanced reconditioning equalizer filter chain. The enhanced reconditioning equalizer filter chain could be implemented in digital or analog domain.

Abstract: In one embodiment, a circuit is provided that includes: an impulse generator operable to provide a pulse train; a pulse position modulator having a splitting junction configured to receive the pulse train, the pulse position modulator including a plurality of n transmission lines, wherein n is an integer, the n transmission lines being selectably coupled in parallel between the splitting junction and a combining junction, the impulse generator driving each transmission line having a unique delay such that if the transmission line is selected, each pulse received at the splitting junction is uniquely delayed into a delayed pulse, whereby if all the transmission lines are selected, each pulse received at the splitting junction is uniquely delayed into a corresponding plurality of n delayed pulses; and a controller operable to select the transmission lines responsive to received words of n bits in length, each word arranged from a first bit to an nth bit, and wherein the transmission lines are arranged from a fi

Abstract: An OFDM telecommunications system includes a transmitter and a receiver. The receiver includes a canceller configured to reduce inter-carrier interference (ICI) in an OFDM symbol in the frequency domain.

Abstract: An apparatus and method for improving a symbol error rate of an M-ary phase shift keying (M-PSK) system having a quadrature error are provided. The apparatus includes: a conversion parameter detector that detects a conversion parameter and converts a symbol decision region using the quadrature error and at least one pair of first received symbols; and a converter & determiner converting a pair of second received symbols using the detected conversion parameter, and determining a transmission symbol according to a symbol of the converted pair of second received symbols. An increase in a symbol error rate due to the quadrature error can be prevented and the quadrature error can be easily estimated.