Patents Examined by Mohammad M Choudhry
  • Patent number: 10566524
    Abstract: Methods of forming the MRAM generally include forming an array of MTJ having sub-lithographic dimensions. The array can be formed by providing a substrate including a MTJ material stack including a reference ferromagnetic layer, a tunnel barrier layer, and a free ferromagnetic layer on an opposite side of the tunnel barrier layer. A hardmask layer is deposited onto the MTJ material stack. A first sidewall spacer is formed on the hardmask layer in a first direction. A second sidewall spacer is formed over the first sidewall in a second direction, wherein the first direction is orthogonal to the second direction. The second sidewall spacer intersects the first sidewall spacer. The first sidewall spacer is processed using the second sidewall spacer as mask to form a pattern of oxide pillars having sub-lithographic dimensions. The pattern of oxide pillars are transferred into the MTJ stack to form the array.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: February 18, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anthony J. Annunziata, Babar A. Khan, Chandrasekara Kothandaraman, John R. Sporre
  • Patent number: 10559461
    Abstract: Methods are provided for conducting a deposition on a semiconductor substrate by selectively depositing a material on the substrate. The substrate has a plurality of substrate materials, each with a different nucleation delay corresponding to the material deposited thereon. Specifically, the nucleation delay associated with a first substrate material on which deposition is intended is less than the nucleation delay associated with a second substrate material on which deposition is not intended according to a nucleation delay differential, which degrades as deposition proceeds. A portion of the deposited material is etched to reestablish the nucleation delay differential between the first and the second substrate materials. The material is further selectively deposited on the substrate.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: February 11, 2020
    Assignee: LAM RESEARCH CORPORATION
    Inventors: Kapu Sirish Reddy, Meliha Gozde Rainville, Nagraj Shankar, Dennis M. Hausmann, David Charles Smith, Karthik Sivaramakrishnan, David W. Porter
  • Patent number: 10553732
    Abstract: The present invention relates to a conductive paste and a method for producing solar cell by using the same. The conductive paste comprises at least silver powders and a composite glass frit comprising a first type of glass frit containing lead oxides and silicon oxides and a second type of glass frit containing tellurium oxides and zinc oxides wherein the first type of glass frit and the second type of glass frit are in a weight ratio of 93:7 to 44:56.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: February 4, 2020
    Assignee: GIGA SOLAR MATERIALS CORP.
    Inventors: Chih-Hsien Yeh, Po-Yang Shih, Jen-Ren Shen, Peng-Sheng Tseng
  • Patent number: 10529721
    Abstract: A method for forming a boron-doped silicon germanium film on a base film in a surface of an object to be processed includes: forming a seed layer by adsorbing a chlorine-free boron-containing gas to a surface of the base film; and forming a boron-doped silicon germanium film on the surface of the base film to which the seed layer is adsorbed by using a silicon raw material gas, a germanium raw material gas, and a boron doping gas through a chemical vapor deposition method.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: January 7, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Mitsuhiro Okada
  • Patent number: 10529559
    Abstract: There is provided a method of manufacturing a semiconductor device, which includes: forming a silicon film inside a recess formed in a surface of a workpiece by supplying a film forming gas containing silicon to the workpiece; subsequently, supplying a process gas, which includes a halogen gas for etching the silicon film and a roughness suppressing gas for suppressing roughening of a surface of the silicon film after being etched by the halogen gas, to the workpiece; etching the silicon film formed on a side wall of the recess to enlarge an opening width of the recess by applying thermal energy to the process gas and activating the process gas; and subsequently, filling silicon into the recess by supplying the film forming gas to the workpiece and depositing silicon on the silicon film remaining in the recess.
    Type: Grant
    Filed: June 15, 2017
    Date of Patent: January 7, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Mitsuhiro Okada
  • Patent number: 10517179
    Abstract: Provided is a material composition and method that includes forming a patterned resist layer on a substrate. The patterned resist layer has a first pattern width, and the patterned resist layer has a first pattern profile having a first proportion of active sites. In some examples, the patterned resist layer is coated with a treatment material. In some embodiments, the treatment material bonds to surfaces of the patterned resist layer to provide a treated patterned resist layer having a second pattern profile with a second proportion of active sites greater than the first proportion of active sites. By way of example, and as part of the coating the patterned resist layer with the treatment material, a first pattern shrinkage process may be performed, where the treated patterned resist layer has a second pattern width less than a first pattern width.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: December 24, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Siao-Shan Wang, Cheng-Han Wu, Ching-Yu Chang, Chin-Hsiang Lin
  • Patent number: 10505017
    Abstract: A semiconductor device and methods of formation are provided. The semiconductor device includes a gate over a channel portion of a fin. The fin includes a first active area of the fin having a first active area top surface coplanar with a first shallow trench isolation (STI) top surface of a first STI portion of STI, and a second active area of the fin having a second active area top surface coplanar with a second STI top surface of a second STI portion of the STI. The method herein negates a need to recess at least one of the fin, the first STI portion or the second STI portion during device formation. Negating a need to recess at least one of the fin, the first STI portion or the second STI portion enhances the semiconductor device formation and is more efficient than a semiconductor device formation that requires the recessing of at least one of a fin, a first STI portion or a second STI portion.
    Type: Grant
    Filed: July 3, 2017
    Date of Patent: December 10, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Blandine Duriez, Mark van Dal
  • Patent number: 10497622
    Abstract: A semiconductor chip manufacturing method includes preparing a semiconductor wafer including a front surface on which a bump is exposed, a rear surface located at a side opposite to the front surface, a plurality of element regions in each of which the bump is formed, and a dividing region defining each of the element regions, forming a mask which covers the bump and has an opening exposing the dividing region on the surface of the semiconductor wafer by spraying liquid which contains raw material of the mask along the bump by a spray coating method, and singulating the semiconductor wafer by exposing the surface of the semiconductor wafer to first plasma and etching the dividing region, which is exposed to the opening, until the rear surface is reached in a state where the bump is covered by the mask.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: December 3, 2019
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Shogo Okita, Mitsuru Hiroshima, Atsushi Harikai, Noriyuki Matsubara, Akihiro Itou
  • Patent number: 10494715
    Abstract: Methods and apparatuses for removing photoresist patterning scum from patterning mandrel structures without damaging other features or structures on a semiconductor substrate are desirable for patterning precision. Methods involve cleaning carbon-containing features on a semiconductor substrate by an atomic layer cleaning (ALC) process to descum the carbon-containing features without substantially modifying feature critical dimensions. The ALC process involves exposing the carbon-containing features to an oxidant or reductant in absence of a plasma, or other energetic activation, to modify scum on the surface of the carbon-containing features. The modified scum on the surface of the carbon-containing features is then exposed to an inert gas along with a plasma ignited at a pressure between 0.1 Torr and 10 Torr and a power of less than 200 W to remove the modified scum from the surface of the carbon-containing features.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: December 3, 2019
    Assignee: LAM RESEARCH CORPORATION
    Inventors: Pulkit Agarwal, Purushottam Kumar, Adrien LaVoie
  • Patent number: 10490508
    Abstract: A back alignment mark on a surface of a semiconductor substrate is detected and a resist mask patterned into a circuit pattern corresponding to a surface element structure is formed on a back of the semiconductor substrate. Detection of the back alignment mark is performed by using a detector opposing the back of the semiconductor substrate and measuring contrast based on the intensity of reflected infrared light irradiated from the back of the semiconductor substrate. The back alignment mark is configured by a step formed by the surface of the semiconductor substrate and bottoms of trenches formed from the surface of the semiconductor substrate. A polysilicon film is embedded in the trenches. The back alignment mark has, for example, a cross-shaped planar layout in which three or more trenches are disposed in a direction parallel to the surface of the semiconductor substrate.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: November 26, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Naoko Kodama
  • Patent number: 10483446
    Abstract: An electronic device includes a carrier and a semiconductor chip, wherein the carrier includes a first dielectric layer and a second dielectric layer, a thermal conductivity of the first dielectric layer exceeds a thermal conductivity of the second dielectric layer, the second dielectric layer is arranged on the first dielectric layer and partially covers the first dielectric layer, the semiconductor chip is arranged on the carrier in a mounting area in which the first dielectric layer is not covered by the second dielectric layer, and the carrier includes a solder terminal for electrical contacting arranged on the second dielectric layer.
    Type: Grant
    Filed: August 6, 2015
    Date of Patent: November 19, 2019
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Kok Eng Ng, Wui Chai Chew, Choo Kean Lim, Mardiana Khalid
  • Patent number: 10475764
    Abstract: A method includes bringing into contact respective first sides of a plurality of dies and a die attach film on a major surface of a carrier wafer, and simultaneously heating portions of the die attach film contacting the plurality of dies in order to simultaneously bond the plurality of dies to the die attach film.
    Type: Grant
    Filed: April 14, 2015
    Date of Patent: November 12, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Shing-Chao Chen, Chung-Shi Liu, Ming-Da Cheng
  • Patent number: 10464061
    Abstract: A technique includes forming a gradient channel with width and depth gradients. A mask is disposed on top of a substrate. The mask is patterned with at least one elongated channel pattern having different elongated channel pattern widths. A channel is etched in the substrate in a single etching step, the channel having a width gradient and a corresponding depth gradient both simultaneously etched in the single etching step according to the different elongated channel pattern widths in the mask.
    Type: Grant
    Filed: April 12, 2016
    Date of Patent: November 5, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORTAION
    Inventors: Jingwei Bai, Qinghuang Lin, Gustavo A. Stolovitzky, Chao Wang, Deqiang Wang
  • Patent number: 10461243
    Abstract: Techniques for configuring the layers included in the free portion of a spin-torque magnetoresistive device are presented that allow for characteristics of the free portion to be tuned to meet the needs of various applications. In one embodiment, high data retention is achieved by balancing the perpendicular magnetic anisotropy of the ferromagnetic layers in the free portion. In other embodiments, imbalanced ferromagnetic layers provide for lower switching current for the magnetoresistive device. In various embodiments, different coupling layers can be used to provide exchange coupling between the ferromagnetic layers in the free portion, including oscillatory coupling layers, ferromagnetic coupling layers using materials that can alloy with the neighboring ferromagnetic layers, and discontinuous layers of dielectric material such as MgO that result in limited coupling between the ferromagnetic layers and increases perpendicular magnetic anisotropy (PMA) at the interface with those layers.
    Type: Grant
    Filed: February 5, 2018
    Date of Patent: October 29, 2019
    Assignee: Everspin Technologies, Inc.
    Inventors: Han-Jong Chia, Jon Slaughter
  • Patent number: 10453815
    Abstract: Methods and apparatus for solder connections. An apparatus includes a substrate having a conductive terminal on a surface; a passivation layer overlying the surface of the substrate and the conductive terminal; an opening in the passivation layer exposing a portion of the conductive terminal; at least one stud bump bonded to the conductive terminal in the opening and extending in a direction normal to the surface of the substrate; and a solder connection formed on the conductive terminal in the opening and enclosing the at least one stud bump. Methods for forming the solder connections are disclosed.
    Type: Grant
    Filed: December 5, 2016
    Date of Patent: October 22, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Hao-Yi Tsai, Chien-Hsiun Lee, Chung-Shi Liu, Hsien-Wei Chen
  • Patent number: 10438799
    Abstract: A method of fabricating semiconductor devices includes sequentially forming a gate layer and a mandrel layer on a substrate, forming a first photoresist on the mandrel layer, forming a mandrel pattern by at least partially removing the mandrel layer using the first photoresist as a mask, forming a spacer pattern that comprises a first mandrel spacer located on a side of a first mandrel included in the mandrel pattern and a second mandrel spacer located on the other side of the first mandrel, forming a sacrificial layer that covers the first and second mandrel spacers after removing the mandrel pattern, forming a second photoresist including a bridge pattern overlapping parts of the first and second mandrel spacers on the sacrificial layer; and forming a gate pattern by at least partially removing the gate layer using the first and second mandrel spacers and the second photoresist as a mask.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: October 8, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang Jine Park, Yong Sun Ko, In Seak Hwang
  • Patent number: 10424510
    Abstract: A method for filling a through hole with solder includes mounting a substrate having a through hole formed therein on a permeable barrier layer having pores that enable gas to flow through the permeable barrier. A solder source is positioned over the through hole. Molten solder is delivered in the through hole with a positive pressure from the solder source such that gas in the through holes passes the permeable barrier while the molten solder remains in the through hole.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: September 24, 2019
    Assignee: International Business Machines Corporation
    Inventors: Toyohiro Aoki, Akihiro Horibe, Kuniaki Sueoka, Kazushige Toriyama
  • Patent number: 10424481
    Abstract: A method of forming a semiconductor device structure comprises forming a preliminary structure comprising a substrate, a photoresist material over the substrate, and a plurality of structures longitudinally extending through the photoresist material and at least partially into the substrate. The preliminary structure is exposed to electromagnetic radiation directed toward upper surfaces of the photoresist material and the plurality of structures at an angle non-orthogonal to the upper surfaces to form a patterned photoresist material. The patterned photoresist material is developed to selectively remove some regions of the patterned photoresist material relative to other regions of the patterned photoresist material. Linear structures substantially laterally aligned with at least some structures of the plurality of structures are formed using the other regions of the patterned photoresist material. Additional methods of forming a semiconductor device structure are also described.
    Type: Grant
    Filed: November 2, 2018
    Date of Patent: September 24, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Scott E. Sills, Gurtej S. Sandhu
  • Patent number: 10418591
    Abstract: Provided is a light emitting device disposed along a transparent member. The light emitting device includes: an organic electroluminescence panel having a translucent substrate disposed to face the transparent member, a translucent anode disposed on the substrate, an organic material layer disposed on the anode, and a non-translucent cathode disposed on the organic material layer. The organic material layer and the cathode are formed in a form of stripes. The cathode is formed wider than the organic material layer.
    Type: Grant
    Filed: June 15, 2017
    Date of Patent: September 17, 2019
    Assignee: Koito Manufacturing Co., Ltd.
    Inventors: Tomoaki Harada, Masaya Shido, Yoshiro Ito
  • Patent number: 10403589
    Abstract: Various semiconductor workpiece polymer layers and methods of fabricating the same are disclosed. In one aspect, a method of manufacturing is provided that includes applying a polymer layer to a passivation structure of a semiconductor workpiece where the semiconductor workpiece has first and second semiconductor chips separated by a dicing street. A first opening is patterned in the polymer layer with opposing edges pulled back from the dicing street. A mask is applied over the first opening. A first portion of the passivation structure is etched while using the polymer layer as an etch mask.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: September 3, 2019
    Assignee: ATI Technologies ULC
    Inventor: Roden R. Topacio