Abstract: A semiconductor device with reduced power consumption is provided. The semiconductor device includes a transmitter unit, a receiver unit, a bias-outputting unit, and a controller unit. The bias-outputting unit has a plurality of memory units. The plurality of memory units each retains information to determine transmission power. The receiver unit receives a request signal transmitted from a base station and supplies it to the controller unit. The controller unit selects one of the plurality of memory units according to the request signal. The memory unit has an OS transistor and retains information when power supply is stopped.

Abstract: A GaN-HEMT device with a sandwich structure and a method for preparing the same are provided. The GaN-HEMT device includes an epitaxial layer and electrodes, wherein the epitaxial layer includes a GaN channel layer (2) and an AlyGa1-y barrier layer (1), and is arranged from top to bottom; the electrodes include a gate electrode (6), a source electrode (7), a drain electrode (5) and a field plate electrode (10), wherein the field plate electrode (10) and the gate electrode (6) are respectively fabricated on an upper surface and a lower surface of the epitaxial layer, and the field plate electrode (10) extends to a region beyond the epitaxial layer and is connected with the gate electrode (6) to form the sandwich structure, and the source electrode (7) and the drain electrode (5) are respectively located at two ends of the epitaxial layer.

Abstract: A semiconductor memory device includes a semiconductor substrate a gate structure extending in a vertical direction on the semiconductor device, a plurality of charge trap layers spaced apart from each other in the vertical direction and each having a horizontal cross-section with a first ring shape surrounding the gate structure, a plurality of semiconductor patterns spaced apart from each other in the vertical direction and each having a horizontal cross-section with a second ring shape surrounding the plurality of charge trap layers, a source region and a source line at one end of each of the plurality of semiconductor patterns in a horizontal direction, and a drain region and a drain line at an other end of each of the plurality of semiconductor patterns in the horizontal direction. The gate structure may include a gate insulation layer and a gate electrode layer.

Abstract: Methods and systems for measuring a complex semiconductor structure based on measurement data before and after a critical process step are presented. In some embodiments, the measurement is based on x-ray scatterometry measurement data. In one aspect, a measurement is based on fitting combined measurement data to a simplified geometric model of the measured structure. In some embodiments, the combined measurement data is determined by subtraction of a measured diffraction pattern before the critical process step from a measured diffraction pattern after the critical process step. In some embodiments, the simplified geometric model includes only the features affected by the critical process step. In another aspect, a measurement is based on a combined data set and a trained signal response metrology (SRM) model. In another aspect, a measurement is based on actual measurement data after the critical process step and simulated measurement data before the critical process step.

Abstract: A display substrate and a display device are provided. The first display region includes a first light-emitting element, and allows light from the first side to be at least partially transmitted to the second side. The first winding portion of the first signal line extends along a curve, the first winding portion, the first bending portion, and the first connecting portion are located in the second display region. The first signal line is configured to transmit a first driving signal to the first pixel circuit to drive the first light-emitting element to emit light. The second signal line is configured to transmit a second driving signal to the second pixel circuit and the third pixel circuit to drive the second light-emitting element and the third light-emitting element to emit light. The third signal line is floating, and is in the second display region and extends along the first direction.

Abstract: A charge trapping non-volatile organic memory device according to the present invention has a structure in which an organic matter-based blocking layer, a trapping layer, and a tunneling layer are sequentially positioned between a gate and an organic semiconductor layer positioned on an insulating substrate, the trapping layer including a metal oxide and a polymer, and has an organic-inorganic composite film in which the metal oxide is dispersed in a polymer matrix in units of atoms.

Abstract: A capacitor includes: a bottom electrode; a top electrode over the bottom electrode; a dielectric film between the bottom electrode and the top electrode; and a doped Al2O3 film between the top electrode and the dielectric film, wherein the doped Al2O3 film includes a first dopant, and an oxide including the same element as the first dopant has a higher dielectric constant than a dielectric constant of Al2O3.

Abstract: A first gate electrode is formed on a semiconductor substrate via a first insulating film containing a metal element. A sidewall insulating film is formed on a side surface of the first gate electrode. A second gate electrode is formed on the semiconductor substrate via a second insulating film. The second gate electrode is formed so as to adjacent to the first gate electrode via the second insulating film. The second insulating film is made of a stacked film having a third insulating film, a fourth insulating film having a charge accumulating function, and a fifth insulating film. The third insulating film is formed on the semiconductor substrate as a result of an oxidation of a portion of the semiconductor substrate, and formed on the side surface of the first gate electrode as a result of an oxidation of the sidewall insulating film, by the thermal oxidation treatment.

Abstract: Implementations of a semiconductor substrate singulation process may include applying a fluid jet to a material of a die street of a plurality of die streets included in a semiconductor substrate where the semiconductor substrate may include: a plurality of die separated by the plurality of die streets; and a plurality of die support structures coupled thereto; and singulating the plurality of die and the plurality of die support structures at the plurality of die streets using the fluid jet. The fluid jet may be moved only along a length of the die street.

Abstract: The present disclosure provides a semiconductor structure and a method for preparing it. After planarization of the Cu layer, by means of wet etch process, Cu residues near an edge of a Cu post can be effectively removed, and a first height difference is configured to be between the Cu post and an insulating layer. Further, an Si substrate is then dry etched, so that a second height difference is configured to be between the Si substrate and the insulating layer, and the second height difference is arranged to be greater than the first height difference. In this way, a connection of Cu inside and outside the insulating layer may be further avoided, thereby effectively avoiding an influence on electrical properties of a device.

Abstract: An apparatus for in-situ etching monitoring in a plasma processing chamber includes a continuous wave broadband light source, an illumination system configured to illuminate an area on a substrate with an incident light beam being directed from the continuous wave broadband light source at normal incidence to the substrate, a collection system configured to collect a reflected light beam being reflected from the illuminated area on the substrate, and to direct the reflected light beam to a first light detector, and a controller. The controller is configured to determine a property of the substrate or structures formed thereupon based on a reference light beam and the reflected light beam, and control an etch process based on the determined property. The reference light beam is generated by the illumination system by splitting a portion of the incident light beam and directed to a second light detector.

Abstract: A semiconductor module includes a semiconductor device that includes first and second fin bases having first and second connecting portions and a resin for sealing the outer peripheral side surfaces of first to fourth conductors, and a flow path forming body connected to the first and second connecting portions of the first and second fin bases. A first elastically deformed portion, which is elastically deformed, is provided such that a distance in a thickness direction between the outer peripheral ends of the first and second connecting portions becomes smaller than a distance in a thickness direction between intermediate portions of the first and second connecting portions. The resin is filled between the first and second connecting portions of the first and second fin bases are filled with the resin therebetween.

Abstract: A silicon-oxide-nitride-oxide-silicon (SONOS) memory cell includes a memory gate, a dielectric layer, two charge trapping layers and two selective gates. The memory gate is disposed on a substrate. The two charge trapping layers are at two ends of the dielectric layer, and the charge trapping layers and the dielectric layer are sandwiched by the substrate and the memory gate. The two selective gates are disposed at two opposite sides of the memory gate, thereby constituting a two bit memory cell. The present invention also provides a method of forming said silicon-oxide-nitride-oxide-silicon (SONOS) memory cell.

Abstract: A semiconductor memory device includes a substrate; a control gate disposed on the substrate; a source diffusion region disposed in the substrate and on a first side of the control gate; a select gate disposed on the source diffusion region, wherein the select gate has a recessed top surface; a charge storage structure disposed under the control gate; a first spacer disposed between the select gate and the control gate and between the charge storage structure and the select gate; a wordline gate disposed on a second side of the control gate opposite to the select gate; a second spacer between the wordline gate and the control gate; and a drain diffusion region disposed in the substrate and adjacent to the wordline gate.

Abstract: A 3-dimensional flash memory device and methods of fabricating and driving the same are provided. The device includes: a channel layer extending over a substrate in a first direction perpendicular to a surface of the substrate; an information storing layer extending along a sidewall of the channel layer in the first direction; control gates each surrounding the channel layer, with the information storing layer between the channel layer and the control gates; an insulating layer being between the control gates in the first direction and separating the control gates from each other; a fixed charge region disposed at an interface of the insulating layer and the information storing layer or in a portion of the information storing layer between the control gates in the first direction; and a doped region induced by the fixed charge region and disposed at a surface of the channel layer facing the fixed charge region.

Abstract: When a voltage is applied to a semiconductor element formed into a semiconductor substrate for evaluating the electrical characteristic of the semiconductor element, partial discharge between the semiconductor element and an inter-element portion, adhesion of a foreign substance to the semiconductor substrate, and formation of a trace of a component in the semiconductor substrate are prevented. A semiconductor device includes a semiconductor substrate and a discharge inhibitor. The semiconductor substrate includes a plurality of semiconductor elements and an inter-element portion. The semiconductor elements are arranged in a spreading direction of the semiconductor substrate. The inter-element portion is between adjacent semiconductor elements among the semiconductor elements. The discharge inhibitor is bonded not to a surface of a center of each semiconductor element among the semiconductor elements but to a surface of the inter-element portion. The discharge inhibitor is made of an insulator.

Abstract: Some embodiments include integrated memory. The integrated memory includes a first series of first conductive structures and a second series of conductive structures. The first conductive structures extend along a first direction. The second conductive structures extend along a second direction which crosses the first direction. Pillars of semiconductor material extend upwardly from the first conductive structures. Each of the pillars includes a lower source/drain region, an upper source/drain region, and a channel region between the lower and upper source/drain regions. The lower source/drain regions are coupled with the first conductive structures. Insulative material is adjacent sidewall surfaces of the pillars. The insulative material includes ZrOx, where x is a number greater than 0. The second conductive structures include gating regions which are spaced from the channel regions by at least the insulative material. Storage elements are coupled with the upper source/drain regions.

Abstract: A manufacturing method of a semiconductor device includes the following steps. A singulation process is performed to a semiconductor wafer for forming semiconductor dies and includes a first cutting step, a thinning step, and a second cutting step. The first cutting step is configured to form first openings in the semiconductor wafer by etching. A portion of the semiconductor wafer is located between each first opening and a back surface and removed by the thinning step. Each first opening penetrates through the semiconductor wafer after the thinning step. The second cutting step is configured to form second openings. Each second opening penetrates through the semiconductor wafer for separating the semiconductor dies. A semiconductor die includes two first side surfaces opposite to each other and two second side surfaces opposite to each other. A roughness of each first side surface is different from a roughness of each second side surface.

Abstract: Described is selective deposition of a silicon nitride (SiN) trap layer to form a memory device. A sacrificial layer is used for selective deposition in order to permit selective trap deposition. The trap layer is formed by deposition of a mold including a sacrificial layer, memory hole (MH) patterning, sacrificial layer recess from MH side, forming a deposition-enabling layer (DEL) on a side of the recess, and selective deposition of trap layer. After removing the sacrificial layer from a slit pattern opening, the deposition-enabling layer (DEL) is converted into an oxide to be used as blocking oxide.

Abstract: In the highly efficient fabrication processes for HNOR arrays provided herein, the channel regions of the storage transistors in the HNOR arrays are protected by a protective layer after deposition until the subsequent deposition of a charge-trapping material before forming local word lines. Both the silicon for the channel regions and the protective material may be deposited in amorphous form and are subsequently crystallized in an anneal step. The protective material may be silicon boron, silicon carbon or silicon germanium. The protective material induces greater grain boundaries in the crystallized silicon in the channel regions, thereby providing greater charge carrier mobility, greater conductivity and greater current densities.