Abstract: Methods, systems, and devices for cache block budgeting techniques are described. In some memory systems, a controller may configure a memory device with a cache. The cache may include a first subset of blocks configured to statically operate in a first mode and a second subset of blocks configured to dynamically switch between operating in the first mode and a second mode. A block operating in the second mode may be configured to store relatively more bits per memory cell than a block operating in the first mode. The controller may track and store, for each block of the second subset of blocks, a respective ratio of cycles performed in the first mode to cycles performed in the second mode. The controller may select a block from the second subset of blocks to switch between modes responsive to a trigger and based on the respective ratio for the block.

Abstract: A processing system includes a processor, a memory, and an operating system that are used to allocate a page table caching memory object (PTCM) for a user of the processing system. An allocation of the PTCM is requested from a PTCM allocation system. In order to allocate the PTCM, a plurality of physical memory pages from a memory are allocated to store a PTCM page table that is associated with the PTCM. A lockable region of a cache is designated to hold a copy of the PTCM page table, after which the lockable region of the cache is subsequently locked. The PTCM page table is populated with page table entries associated with the PTCM and copied to the locked region of the cache.

Abstract: Methods, systems, and devices for repair operation techniques are described. A memory device may detect a failure of a read operation associated with a physical row address of a memory die. The memory device may store information associated with the physical row address before performing a media management operation and after detecting the failure. Additionally or alternatively, the memory device may initiate a counter based on detecting the failure and may increment a value of the counter for each media management operation performed after detecting the failure. The memory device may send a command or other information to perform a repair operation for the physical row address. The memory device may determine the physical row address for the repair operation (e.g., despite media management operations) based on the stored information or the value of the counter, and may perform the repair operation on the physical row address.

Abstract: Systems, methods, and apparatus related to a memory system that manages an interface for a volatile memory device and a non-volatile memory device to control memory system power. In one approach, a controller evaluates a demand on memory performance. If the demand of a current computation task needed by the host is high, a DRAM device is powered-up to meet the demand. Otherwise, if the non-volatile memory device is adequate to meet the demand, the DRAM memory is partially or fully-powered down to save power. In another approach, a task performed for a host device uses one or more resources of a first memory device (e.g., DRAM). A performance capability of a second memory device (e.g., NVRAM) is determined. A controller of the memory system determines whether the performance capability of the second memory device is adequate to service the task.

Abstract: A method for use in a first storage array, comprising: detecting whether a second storage array has designated the first storage array as a locally-preferred storage array, the detecting being performed when a first link between the second storage array and a witness node is down; setting a value of a first configuration setting to indicate that the first storage array is designated as a system-preferred storage array, the value of the first configuration setting being stored in a memory of the first storage array, the value of the first configuration setting being set only when the second storage array has designated the first storage array as a locally-preferred storage array; detecting, by the first storage array; and when the second link is down, assuming one of an active role or a passive role based, at least in part, on the value of the first configuration setting.

Abstract: The present disclosure generally relates to data storage devices and related methods that use secure host memory buffers (HMBs) and low latency operations. A controller of the data storage device is configured to access the HMB, where the HMB stores a Merkle Tree. When the HMB is initialized, the controller determines a number of hash levels of the Merkle Tree. Each hash level of the Merkle Tree comprises one or more hashes. When storing location data in a target data block of the Merkle Tree, the controller is configured to initialize only the hashes along a path between a top hash and the target data block. Each hash along the path has a non-initialized hash coupled to a common hash. The non-initialized hash is programmed with a non-initialized bit, such that only the relevant hashes and data blocks are initialized.

Abstract: An apparatus (2) comprises processing circuitry (4) to perform speculative execution of instructions; a main cache storage region (30); a speculative cache storage region (32); and cache control circuitry (34) to allocate an entry, for which allocation is caused by a speculative memory access triggered by the processing circuitry, to the speculative cache storage region instead of the main cache storage region while the speculative memory access remains speculative. This can help protect against potential security attacks which exploit cache timing side-channels to gain information about allocations into the cache caused by speculative memory accesses.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to evict in a dual datapath victim cache system. An example apparatus includes a cache storage, a cache controller operable to receive a first memory operation and a second memory operation concurrently, comparison logic operable to identify if the first and second memory operations missed in the cache storage, and a replacement policy component operable to, when at least one of the first and second memory operations corresponds to a miss in the cache storage, reserve an entry in the cache storage to evict based on the first and second memory operations.

Abstract: A method may include receiving, by a first computing system, a first request from a first client device to download content. The method may further include receiving, by the first computing system from a second computing system, first information. The first information may be indicative of a first version of the content that the first client device is authorized to download and a source from which the first version of the content can be downloaded. The method may also include determining, by the first computing system and based at least in part on the first information, that the first version of the content is already present on the first computing system. The method may additionally include sending, from the first computing system to the first client device, the first version of the content or second information, the second information indicative of the first version of the content.

Abstract: Examples described herein relate to a system including a first management system having a primary memory including a free memory, a used memory, and a loosely reserved memory, where the loosely reserved memory comprises cache memory having a reclaimable memory; and a processing resource coupled to the primary memory. The processing resource may monitor an amount of the used memory and an amount of an available memory during runtime of the first management system. Further, the processing resource may enable a synchronized reboot of the first management system if the amount of the used memory is greater than a memory exhaustion first threshold or the amount of the available memory is less than a memory exhaustion second threshold, wherein the memory exhaustion first threshold and the memory exhaustion second threshold are determined based on usage of the reclaimable memory and a number of major page faults.

Abstract: Disclosed embodiments relate to a shared read request (SRR) using a common request tracker (CRT) as a temporary cache. In one example, a multi-core system includes a memory and a memory controller to receive a SRR from a core when a Leader core is not yet identified, allocate a CRT entry and store the SRR therein, mark it as a Leader, send a read request to a memory address indicated by the SRR, and when read data returns from the memory, store the read data in the CRT entry, send the read data to the Leader core, and await receipt, unless already received, of another SRR from a Follower core, the other SRR having a same address as the SRR, then, send the read data to the Follower core, and deallocate the CRT entry.

Abstract: The present disclosure is directed to systems and methods of implementing a neural network using in-memory, bit-serial, mathematical operations performed by a pipelined SRAM architecture (bit-serial PISA) circuitry disposed in on-chip processor memory circuitry. The on-chip processor memory circuitry may include processor last level cache (LLC) circuitry. The bit-serial PISA circuitry is coupled to PISA memory circuitry via a relatively high-bandwidth connection to beneficially facilitate the storage and retrieval of layer weights by the bit-serial PISA circuitry during execution. Direct memory access (DMA) circuitry transfers the neural network model and input data from system memory to the bit-serial PISA memory and also transfers output data from the PISA memory circuitry to system memory circuitry.

Abstract: A method of operation of a storage system includes: establishing a virtual storage device 1 including allocating portions of a storage media 1, a storage media 2, a storage media N, or a combination thereof including writing data blocks to the virtual storage device 1; determining a pinning status for the data blocks; pinning the data blocks to a logical block address (LBA) range until the pinning status indicates an unpinning of the data blocks; and relocating the data blocks to the storage media 1, the storage media 2, the storage media N, or the combination thereof within the virtual storage device 1 when the pinning status indicates unpinned.

Abstract: Hash-based application programming interface (API) importing can be prevented by allocating a name page and a guard page in memory. The name page and the guard page being associated with (i) an address of names array, (ii) an address of name ordinal array, and (iii) an address of functions array that are all generated by an operating system upon initiation of an application. The name page can then be filled with valid non-zero characters. Thereafter, protections on the guard page can be changed to no access. An entry is inserted into the address of names array pointing to a relative virtual address corresponding to anywhere within the name page. Access to the guard page causes the requesting application to terminate. Related apparatus, systems, techniques and articles are also described.

Abstract: Multi-cache-based digital output generation is provided. A system receives data objects that include fields from a remote data source. The system sorts the data objects based on a field to generate a sorted data set. The system cleans the sorted data set to generate a clean data set based on a policy. The system receives a request for a type of digital output based on the data objects received from the data source and loads a portion of the clean data set to a first level cache. The system selects a machine learning model configured for the type of digital output, and loads a primary cache with a subset of fields stored in the first level cache selected based on the machine learning model. The system generates, based on the first level cache being complete, digital output corresponding to the type of digital output from data in the primary cache.

Abstract: Methods, systems, and devices for read operations for regions of a memory device are described. In some examples, a memory device may include a first cache for storing mappings between logical addresses and physical addresses of the memory device, and a second cache for storing indices associated with entries removed from the first cache. The memory device may include a controller configured to load mappings to the first cache upon receiving read commands. When the first cache is full, and when the memory device receives a read command, the controller may remove an entry from the first cache and may store an index associated with the removed entry to the second cache. The controller may then transmit a mapping associated with the index to a host device for use in a HPB operation.

Abstract: A storage access request to access a solid state drive (SSD) is received. A storage access timer is set with a time duration, where the time duration is based on a desired performance of the SSD. A non-volatile memory command associated with the storage access request is sent to non-volatile memory. The storage access timer is started. A determination is made whether the non-volatile memory completed execution of the non-volatile memory command after the storage access timer indicates that the time duration elapsed. An indication that the storage access request is complete is sent to a host if the non-volatile memory completed execution of the non-volatile memory command. Alternatively, the storage access timer is reset with the time duration if the non-volatile memory has not completed execution of the non-volatile memory command.

Abstract: A memory system may include a cache memory, a nonvolatile memory, a write back wait queue, and a controller. To evict an eviction cache entry including a target transaction ID from the memory cache to the nonvolatile memory, the controller performs write back operations on cache entries respectively corresponding to waiting entries at a head of the write back wait queue until a waiting entry including the target transaction ID arrives at the head of the write back wait queue, and then performs a write back operation on the eviction cache entry.

Abstract: A method comprising: receiving a request to write data at a virtual location; writing the data to a physical location on a persistent storage device; and recording a mapping from the virtual location to the physical location; wherein the physical location corresponds to a next free block in a sequence of blocks on the persistent storage device.

Abstract: Data processing techniques comprise, in response to determining that a storage unit storing first data blocks is damaged, determining storage units associated with the storage unit, and obtaining second data blocks from the storage units, where the second data blocks and the first data blocks are generated by applying to data an error correction code in a first format. The method further comprises recovering the first data blocks based on the second data blocks. In addition, the method comprises generating error correction blocks by applying an error correction code in a second format to the recovered first data blocks, where the second format is different from the first format. The above techniques can reduce input/output operations and shortens the recovery time of data blocks, and further can reduce the risk of data loss even in an extremely bad situation.