Patents Examined by Mohammad S Hasan
  • Patent number: 10884630
    Abstract: A storage system includes a controller and a nonvolatile memory drive, in which the controller transmits a write request that designates a volume identifier of a volume to be provided to a host, to the nonvolatile memory drive; the nonvolatile memory drive exclusively allocates a free block selected from a plurality of blocks to the volume identifier; write data of the write request is written to the free block; when the write data is update write data, an area that stores data to be updated is changed to an invalid data area; and after valid data of a block including the invalid data area is migrated to another block, all data of the block including the invalid data area is erased.
    Type: Grant
    Filed: April 13, 2017
    Date of Patent: January 5, 2021
    Assignee: Hitachi, Ltd.
    Inventors: Koji Hosogi, Naoya Okada, Akifumi Suzuki, Hideyuki Koseki, Masahiro Tsuruya
  • Patent number: 10877788
    Abstract: Examples include a processor including fetch circuitry to fetch a guest physical address translation instruction having a format with fields to specify at least an opcode and locations of a source vector and a destination vector, decode circuitry to decode the fetched guest physical address translation instruction, and execution circuitry to execute the decoded guest physical address translation instruction. Execution of the decoded guest physical address translation instruction includes comparing guest physical addresses of the source vector with base and end addresses of a selected memory region, masking a guest physical address of the source vector if the guest physical address is in the selected memory region, translating the masked guest physical addresses into host addresses, and storing the host addresses into the destination vector.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: December 29, 2020
    Assignee: Intel Corporation
    Inventors: Fan Zhang, Bruce Richardson
  • Patent number: 10860483
    Abstract: A technique handles metadata corruption to avoid data unavailability. The technique involves performing metadata evaluation operations on metadata describing pages of written data in a data-log that holds data en route to volumes in secondary storage. The technique further involves, while results of the metadata evaluation operations indicate that there is no corrupt metadata, flushing the pages of written data from the data-log to the volumes in the secondary storage. The technique further involves, in response to a result of a particular metadata evaluation operation indicating that metadata for a particular page of written data in the data-log is corrupt, quarantining the particular page of written data from the data-log to a containment cache to enable further flushing of other pages of written data from the data-log to the volumes in the secondary storage.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: December 8, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: Leron Fliess, Nimrod Shani, Ronen Gazit
  • Patent number: 10754559
    Abstract: A first storage system is configured to participate in a replication process with a second storage system using an active-active configuration. A request for a time-to-live (TTL) grant is received in the first storage system from the second storage system. The first storage system computes an estimate of a difference between local times in the respective first and second storage systems, utilizes the computed estimate in the first storage system to determine a TTL expiration time in the local time in the second storage system, and sends the TTL grant with the TTL expiration time to the second storage system in response to the request. The computed estimate of the difference between the local times in the respective first and second storage systems is illustratively utilized in the first storage system to determine a range for the local time in the second storage system.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: August 25, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: David Meiri, Anton Kucherov
  • Patent number: 10747667
    Abstract: An aspect of memory management is provided. An aspect includes evaluating performance parameters of caches of a control module. The caches of the control module have two types of entries: address, hash, and physical location values, and address-to-short-hash (A2SH) values. An aspect further includes evaluating performance parameters of caches of a data module of the multi-layer cache system. The caches of the data module cache include three types of entries: a short-hash-to-physical address, a full-hash-and-short-hash-to-physical address, and a filter mechanism. An aspect further includes predicting an effect that a modification to a size of one of the caches o is on performance of operations at the multi-level cache based on results of the calculating the performance parameters of the caches. Upon estimating an increase in performance, an aspect includes increasing allocation to the cache is determined to have increased performance responsive to the estimating, and decreasing allocation from another cache.
    Type: Grant
    Filed: November 2, 2018
    Date of Patent: August 18, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: Assaf Natanzon, Amitai Alkalay, Zvi Schneider