Abstract: A semiconductor device enabling word lines to be arranged at close intervals, comprising a plurality of memory transistors arranged in an array and a plurality of word lines serving also as gate electrodes of memory transistors in a same row, extending in a row direction, and repeating in a column direction, where insulating films are formed between the plurality of word lines to insulate and isolate the word lines from each other and where a dimension of separation of word lines is defined by the thickness of the insulating films.

Abstract: A light-emitting device comprises a light-emitting unit including a plurality of first connecting pads, a base substrate including a plurality of second connecting pads, and a plurality of conductive bumps that connect the first connecting pads of the light-emitting unit to the second connecting pads of the base substrate. In the manufacturing process, a reflow process is performed to bond the conductive bumps to the first and second connecting pads. The light-emitting unit is configured to emit a first light radiation upon the application of an electric current flow, and the base substrate is configured to emit a second light radiation when stimulated by the first light radiation.

Abstract: A semiconductor device includes a semiconductor path, the semiconductor path including an organic semiconductor material, a first contact to inject charge carriers into the semiconductor path, a second contact to extract charge carriers from the semiconductor path, and a layer including phosphine arranged between the first contact and the semiconductor path and/or between the second contact and the semiconductor path. The phosphine in the layer acts as a charge transfer molecule which makes it easier to transfer charge carriers between contact and organic semiconductor material. As a result, the contact resistance between contact and organic semiconductor material can be reduced considerably.

Abstract: An integrated circuit chip is provided, which includes a bond pad structure. The bond pad structure includes a bond pad, a first metal plate, and a second metal plate. The first metal plate is located under the bond pad. The first metal plate has a first outer profile area. The second metal plate is located under the first metal plate. A cumulative top view outer profile area of the first metal plate and the second metal plate is larger than the first outer profile area of the first metal plate. The second metal plate may have a second outer profile area that is substantially equal to or larger than the first outer profile area. A first vertical axis may extend through a centroid of the first metal plate, and a centroid of the second metal plate may be laterally offset relative to the first vertical axis.

Abstract: A semiconductor memory device comprises a cell capacitor having a first buried contact connected with a semiconductor substrate of a cell region and a first storage node connected with the first buried contact, and a decoupling capacitor for reducing a coupling noise, having a plurality of second buried contacts formed on a semiconductor substrate portion adjacent in the cell region and extended in parallel with each other and a plurality of second storage nodes connected with the second buried contacts.