Abstract: A power reserve apparatus is disclosed. In one embodiment, the power reserve apparatus comprises a first module including a first set of battery cells and a first inter-cell balance adjustment unit configured to use passive balancing to reduce voltage variance among the first set of battery cells. The power reserve apparatus also comprises a second module including a second set of battery cells and a second inter-cell balance adjustment unit configured to use passive balancing to reduce voltage variance among the second set of battery cells. The power reserve apparatus further comprises an inter-module balance adjustment unit configured to use active balancing to reduce voltage variance among the first and second modules.

Abstract: An active charge equilibrium system for lithium battery pack consists a lithium battery pack composed of connecting multiple cells in series, including a multiplex module, control module and multiple equilibrium control module, which each segment of the cells are connected to the multiplex module in sequence, a voltage signal is converted into a digital signal via the control module to compare the voltages of the cells and select the cell with lower voltage. Further, the control module enables the equilibrium control module corresponding to the cell with the lower voltage to work. A pulse width modulator adjusts the output pulse width according to output current and voltage signal from a signal feedback module for controlling current and voltage to charge the cell. As the voltage of the cell reaches a constant current first and a constant voltage second, the control module turns off said equilibrium control module.

Abstract: A method includes obtaining a plurality of design rules for an integrated circuit, including a first set of design rules and a second set of design rules. An automated layout construction process performed on the basis of the first set of design rules but not on the basis of the second set of design rules creates a layout of the integrated circuit. The layout of the integrated circuit is checked for design rule violations wherein at least one member of the second set of design rules is not satisfied. The layout of the integrated circuit is modified for bringing the layout into conformity with each of the plurality of design rules if one or more design rule violations are found in the checking of the integrated circuit.

Abstract: The timing analysis of an integrated chip component using dynamic load sensitive timing feedback constraints maintaining the timing accuracy for all the boundary paths is achieved by capturing a reduced order representation for parasitic load within a component for each of its primary input and primary output along with sensitivities of the arrival time, the slew and the required arrival time to the load representation at the component parent level of hierarchy as part of generating load sensitive feedback constraints. During the out-of-context timing closure of the component, the base load representation and the sensitivities, and an updated load representation enables the calculation of the updated boundary constraint for an accurate timing analysis. The accuracy improvement increases a chip designer productivity during timing closure resulting in a shortened time to take the chip design through timing closure to manufacturing.

Abstract: A method for measuring a surface structure of a chip or a wafer is provided that includes obtaining an image of the surface structure of the chip, and then performing an image extraction on the image to convert the extracted image into a first circuit design file. A standard image is selected to convert into a second circuit design file, and then the standard image and at least one target in the image are compared to obtain a difference therebetween. According to the difference, at least one data of the surface structure may be made, wherein the data is selected from one of line edge roughness (LER), line width roughness (LWR), contact edge roughness (CER), critical dimension (CD), bias, 3 sigma, maximum, minimum, etc. and repeating defect.

Abstract: Universal target based inspection drive metrology includes designing a plurality of universal metrology targets measurable with an inspection tool and measurable with a metrology tool, identifying a plurality of inspectable features within at least one die of a wafer using design data, disposing the plurality of universal targets within the at least one die of the wafer, each universal target being disposed at least proximate to one of the identified inspectable features, inspecting a region containing one or more of the universal targets with an inspection tool, identifying one or more anomalistic universal targets in the inspected region with an inspection tool and, responsive to the identification of one or more anomalistic universal targets in the inspected region, performing one or more metrology processes on the one or more anomalistic universal metrology targets with the metrology tool.

Abstract: A method, system, and computer program product include electronic design automation (EDA) tools used with standard CMOS processes to design and produce radiation-hardened (rad-hard) integrated circuits (ICs) having a predictable level of radiation hardness while maintaining a desired level of performance and tracking circuit area. The tools include rad-hard design rule checking (DRC) decks, rad-hard SPICE models, and rad-hard cell libraries. A rad-hard parasitic components extraction process makes use of rad-hard DRC rules to locate occurrences of parasitic devices, calculate their effects on circuit performance, and return this information to layout and circuit simulation tools. Changes to the layout are suggested and implemented with varying degrees of automation. Some of these tools can be provided as components of a rad-hard process design kit (PDK). They can be used in conjunction with commercial EDA tools to facilitate the incorporation of rad-hard features into new or existing IC designs.

Abstract: A mask data generating method for generating data of a plurality of masks used in a plurality of exposures in which exposure light is irradiated onto a substrate using a mask, and then exposure light is irradiated onto the substrate using another mask. The method includes the steps of obtaining data for a pattern including a plurality of pattern elements, determining formulation of a disposition limitation condition for the pattern elements, analyzing the distance between the pattern elements, determining formulation of the distance limitation condition, and applying a first variable configured to express a number of pattern divisions and a second variable configured to express a distance related to all pattern elements in a cost function and thereby dividing the pattern.

Abstract: Embodiments relate to cross-hierarchy interconnect adjustment. An aspect includes receiving chip layout data corresponding to a chip design, wherein a first portion of a metal stack of the chip design is assigned to a first hierarchy and a second portion of the metal stack is assigned to a second hierarchy based on a contract between the first and second hierarchy. Another aspect includes determining an unused portion of the first portion of the metal stack. Another aspect includes moving an interconnect of the second hierarchy from the second portion of the metal stack that is assigned to the second hierarchy to the unused portion of the first portion of the metal stack in the chip layout data. Another aspect includes performing power recovery on the chip layout data after moving the interconnect based on an amount of slack margin generated in the chip design by the moving of the interconnect.

Abstract: Techniques relate to dynamic complex fault model generation for diagnostics simulation and pattern generation. Inline fabrication parametric data is received, and the inline fabrication parametric data is a collection of physical measurements made on a device under test during a manufacturing fabrication of the device under test. A fault model of defects is generated according to the inline fabrication parametric data, where the fault model is based on a physical design of the device under test combined with the inline fabrication parametric data for the device under test. Test patterns are generated based on the fault model and the inline fabrication parametric data, such that the test patterns are configured to test the device under test in order to obtain results that are based on the inline fabrication parametric data. A simulation is run of the device under test using the results and the inline fabrication parametric data.

Abstract: Provided are an EMI characteristic derivation unit which derives an EMI characteristic radiated from a cable based on design information of a circuit board connected with the cable; a determination standard database which stores an EMI tolerance condition which is a tolerance condition for the EMI characteristic; an EMI condition determination unit which determines whether the EMI characteristic satisfies the EMI tolerance condition; an improvement effect database which stores a modification guideline to modify a configuration of the circuit board necessary to satisfy the EMI tolerance condition when the EMI characteristic does not satisfy the EMI tolerance condition and an improvement effect corresponding to the modification guideline; a restriction item database which stores a restriction item applied when the configuration of the board is modified; and a configuration modification unit which performs the configuration modification of the board in accordance with the modification guideline and the restricti

Abstract: System and methods for estimating a capacity of a battery are presented. In certain embodiments, charge and discharge current throughput data may be separately accumulated during operation of a battery system (e.g., during a charge sustaining operation of vehicle associated with the battery system). Charge and discharge voltage-based state of charge movement data may be further separately accumulated. Upon accumulating sufficient data, estimated charge and discharge battery capacities may be determined based on the accumulated data.

Abstract: Implementations of the present disclosure involve a system and method for load balancing a string of jars. The temperature and voltage of each jar is measured and a target voltage for the jar is set based on the measured temperature. A current is supplied to the jar in order to maintain, increase, or decrease the jar's voltage.

Abstract: A method of providing a photolithography pattern can be provided by identifying at least one weak feature from among a plurality of features included in a photolithography pattern based on a feature parameter that is compared to a predetermined identification threshold value for the feature parameter. A first region of the weak feature can be classified as a first dosage region and a second region of the weak feature can be classified as a second dosage region. Related methods and apparatus are also disclosed.

Abstract: Integrated circuits may be programmed using configuration data to implement desired custom logic circuits. The configuration data may be generated using a logic design system. The logic design system may include first and second compilers and an emulation engine. The first compiler may compile a computer program language description of the logic circuit to generate a hardware description language (HDL) description. The emulation engine may emulate performance of the logic circuit when loaded on a target device and may monitor the emulated performance to generate emulated profile data characterizing the emulated performance of the logic circuit. The first compiler may process the emulated profile data to identify optimizations to perform on the logic circuit and may compile an optimized HDL description. The second compiler may compile optimized configuration data using the optimized HDL.

Abstract: A system, method, and computer program product for automatically reducing the number of Monte Carlo simulation samples required to determine if a design yield is above or below a given yield target with a given confidence. Embodiments perform an initial Monte Carlo based performance modeling using an initial set of statistical samples, and estimate the failure probability of each of the remaining statistical samples based on the performance model. Embodiments then simulate each of the remaining statistical samples with a computer-operated Monte Carlo circuit simulation tool in decreasing failure probability order, wherein the sample most likely to fail is simulated first. Progressive comparisons of the simulated yield against a yield target eventually verify the yield at a required confidence level, halting the simulation and triggering tangible output of the comparison results. A potential ten-fold decrease in overall yield verification time without loss of accuracy may result.

Abstract: Provided is a portable charger connected to a wall electric power source and configured to supply an electric power from the wall electric power source to a load. The portable charger includes a plug, an electric wire, a switch, a first detection unit, a second detection unit, and a control unit. The control unit is configured to supply an electric power through the electric wire to the load when the plug is plugged in the socket and to cut off the supply of the electric power flowing through the electric wire by controlling the switch on the basis of the user's approach that is detected by the first detection unit, and the tensile force that is detected by the second detection unit while the electric power is being supplied.

Abstract: A method, system and computer readable medium for coverage driven generation of stimuli for DUT verification. The method may include receiving, via an input device, a generation model and a coverage model from a user. The method may also include using a processor, identifying a coverage item in the coverage model and finding a corresponding element in the generation model corresponding to the coverage item. The method may further include using a processor translating a coverage requirement associated with the coverage item into a distribution directive; and using a processor, solving the generation model with the distribution directive on the corresponding element, to obtain a set of stimuli.

Abstract: A method for the simulation of a circuit is disclosed. The method may include the determination of parasitic circuit elements, and the determination of one or more operational parameters dependent upon at least the parasitic circuit elements. A model of the parasitic circuit elements may then be generated based upon the one or more operational parameters. The circuit may then be simulated using the model of the parasitic circuit elements to determine a performance level of the circuit. At least one active circuit element may be modified in response to determining that the performance level does not meet a goal.

Abstract: A mobile power device includes a primary rechargeable battery; a primary case covering the primary rechargeable battery; a charging electrical port, exposed to the exterior of the primary case and coupled to the primary rechargeable battery, serving to connect to an external power source for charging the primary rechargeable battery; a first discharging electrical port, exposed to the exterior of the primary case and coupled to the primary rechargeable battery, serving to connect to a load to be powered via the first discharging electrical port; a plurality of first primary electrical contacts, exposed to the exterior of the primary case and coupled to the primary rechargeable battery; and a primary magnetic member, integrally formed with the primary case, being made of ferromagnetic material or ferrimagnetic material.