Abstract: Presented herein are systems, methods, and devices for analyzing a circuit. A netlist is obtained and parsed, where the netlist describes the circuit having one or more branches and one or more nodes. A linear system describing the circuit is obtained and compressed using a hierarchical approach. Compression involves storing off-diagonal sub-blocks in a dense matrix in a low-rank format to reduce the density of the matrix. The linear system is then solved using an iterative operation. An initial guess is used for the voltage at each node and the current through each branch. After performing the first iteration, an initial estimate for the voltage and current is stored and used as the initial guess for the second iteration. The iterative operation is continued until the estimate for the voltage at each node and the current through each branch is sufficiently accurate.

Abstract: A method, system, and computer program product to characterize and adaptively instantiate timing abstracts to perform timing analysis of an integrated circuit include generating an adaptable timing abstract for one or more macro models of a macro, the macro including two or more primitives of a component of the integrated circuit, the adaptable timing abstract being a parameterized timing model with at least one aspect represented by two or more models, and estimating requirements for the timing analysis, the requirements including accuracy, runtime, or memory requirements. Selecting a specific timing abstract, obtained by setting parameters of the adaptable timing abstract, is to perform the timing analysis based on the requirements.

Abstract: A computer-implemented method includes identifying an in initial register-transfer-level description for an integrated circuit design and adding one or more spare latches to the initial register-transfer-level description to yield a modified register-transfer-level description for the integrated circuit design. The computer-implemented method further includes performing placement and routing for the modified register-transfer-level description to yield a gate-level description for the integrated circuit design. The one or more spare latches exist in said gate-level description. The computer-implemented method further includes converting at least one of the one or more spare latches in the gate-level description into a reconfigurable latch filler cell to yield a modified gate-level description for the integrated circuit design and finalizing the integrated circuit design. A corresponding computer program product and computer system are also disclosed.

Abstract: A power tool system includes a power tool, a power tool battery pack and a battery pack charger. The power tool battery pack is separable from and attachable to the power tool, and electrically connectable to the power tool electrical terminals when attached to the power tool. The power tool battery pack has at least one battery cell, a receiver coil, and a control circuit for controlling the amount of power that is provided to the at least one battery cell. The battery pack charger has at least one transmitter coil for generating a magnetic field which induces a voltage in the receiver coil, and a control circuit for controlling the amount of power that is provided to the transmitter coil.

Abstract: Described herein are example charging stations for wirelessly recharging a variety of mobile devices. In some cases, the charging station is configured to receive a location indication of an antenna within the device, to determine a position of the device within the charging station, and to select an antenna from an array of antennas to provide a recharge signal to the device based on the location indication and the position of the device.

Abstract: A battery pack includes a plurality of rechargeable batteries, a sensor, and a battery manager. The sensor obtains motion information of the rechargeable batteries. The motion information includes at least one of first information obtained by sensing whether the rechargeable batteries are in a movement state or in a standstill state or second information on a state in which the rechargeable batteries are inclined. The second information may be obtained based on a change in angle when the rechargeable batteries are in the movement state. The battery manager control charging or discharging of the rechargeable batteries in a charge mode or a discharge mode based on the motion information.

Abstract: Integrated circuit design layout files are partitioned into one or more design layout files containing data for Front-End-Of-Line sub-circuits and one or more design layout files containing data for Back-End-Of-Line sub-circuits. By sending each of the files to a separate foundry for manufacture, an intellectual property owner can ensure integrity of his property as no individual file alone contains sufficient information to deduce the overall function of the integrated circuit.

Abstract: A protection switch circuit includes: an input terminal configured to receive a DC input voltage; an output terminal; a switch provided between the input terminal and the output terminal; a determination circuit configured to compare the input voltage with N threshold voltages (N is a natural number); and a gate controller configured to control the switch based on a comparison result of the determination circuit, wherein the determination circuit includes: an OTPROM (One Time Programmable Read Only Memory) to which N pieces of setting data indicative of each of the N threshold voltages are written under software control, and a comparison circuit configured to compare the input voltage with each of the N threshold voltages according to the N pieces of the setting data written to the OTPROM.

Abstract: The present disclosure relates to a system and method for simulating channels in an electronic circuit design. Embodiments may include receiving, at one or more computing devices, an electronic circuit design including at least one channel. Embodiments may further include transmitting two or more inputs from two or more transmitter drivers on two or more wires to the at least one channel. In some embodiments, the inputs may be distributed across the wires based upon a chordal code. Embodiments may also include generating simulated waveforms based upon the inputs. Embodiments may further include transmitting the simulated waveforms from the channel on the wires to a comparator block. Embodiments may also include comparing the simulated waveforms on the wires at the comparator block to produce two or more simulated outputs. Embodiments may include transmitting the simulated outputs from the comparator block on the wires to two or more post-comparator receivers.

Abstract: A method for redistribution layer routing is proposed. The method at least comprises inputting information regarding a redistribution layer layout, at least one netlist, and a constraint file. Next, it is creating a concentric-circle model based on the information, the netlist and the constraint file. Subsequently, it is assigning at least one pre-assignment net to at least one redistribution layer according to the concentric-circle model. Finally, the redistribution layer routing is performed.

Abstract: A rectification and regulation circuit for a wireless power receiver includes a coil for magnetically coupling to a primary coil of a power transmitter, a full-wave rectifier circuit separate from the power transmitter and a control unit separate from the power transmitter. The full-wave rectifier has a first pair of controllable rectifiers including a first transistor connected to a first terminal of the coil and a second transistor connected to a second terminal of the coil. The control unit is operable to control switching of the transistors of the full-wave rectifier so that the full-wave rectifier (a) generates a rectified output for charging a battery of the wireless power receiver by rectifying current through the coil or voltage across the coil, and (b) regulates the rectified output.

Abstract: Embodiments herein describe a verification process that identifies unate primary inputs in input paths of a property gate. A property gate is logic inserted in a hardware design represented by a netlist which is used to verify the design. Before performing the verification process, a computing system evaluates the netlist to identify the primary inputs in the input paths of the property gate and whether these primary inputs are unate or binate. To do so, in one embodiment, the computing system sets the output of the property gate in an error state and then traverses the input paths of the property gate to identify the values of the logic in the inputs paths that would result in the property gate being in the error state. Based on these polarities, the system can identify the unate and binate primary inputs.

Abstract: A method for fabricating an interposer wafer includes providing at least one mask having printing regions for forming a plurality of interposer designs; selecting an interposer design; and forming the interposer design on a substrate using a plurality of lithographic imaging steps. For each lithographic imaging step, at least one portion of the interposer design is printed by exposing at least one of the printing regions while blocking at least one other of the printing regions.

Abstract: An intelligent battery optimization management and equalization system that also monitors all cells within a battery. The system will ensure all cells are charged to maximum capacity, discharges the full capacity of each cell, perform equalization of charges between all the cells, manages and monitors each cell within a battery pack.

Abstract: The present invention is applied to a charger that charges a rechargeable battery mounted on an electric vehicle. The charger according to the present invention includes an electric power supply unit that supplies electric power to said rechargeable battery; a payment unit that makes payment with electronic money to use said charger; and a control unit, when said control unit is instructed by said electric vehicle to start charging, that instructs said electric power supply unit to start supplying electric power to said rechargeable battery and that instructs said payment unit to make payment with said electronic money.

Abstract: A method for performing wireless charging control of an electronic device and an associated apparatus are provided, where the method includes: determining at least one random value for controlling timing of packet transmission regarding at least one wireless charging report of the electronic device; and based on the aforementioned at least one random value, sending at least one random phase-delay packet, wherein each random phase-delay packet of the aforementioned at least one random phase-delay packet has a random phase-delay with respect to a time slot, and the aforementioned at least one random phase-delay packet is utilized for carrying information of the aforementioned at least one wireless charging report. More particularly, a wireless charging device (e.g. transmitter pad) is arranged to wirelessly charge the electronic device, and based on the aforementioned at least one random value, the electronic device does not obtain information from the wireless charging device through any packet.

Abstract: A computer implemented method of fracturing free form target design into elementary shots for defined roughness of the contour comprises determining a first set of shots which pave the target design and determining a second set of shots to fill the gaps. The dose levels of overlapping shots in the first or second sets of shots are determined so the compounded dose is adequate to the resist threshold, considering the proximity effect of the actual imprint of shots on the insulated target. A dose geometry modulation is applied and rounded shot prints are produced by shots not circular that may overlap. The degree of overlap is determined as a function of desired optimization of fit criteria between a printed contour and the contour of the desired pattern. Placements and dimensions of the shots are determined by a plurality of fit criteria between printed contour and contour of the desired pattern.

Abstract: Passive verification, comprising, receiving a representation of an electronic design comprised at least in part of at least system having at least one subsystem which is analog, collecting at least one input subsystem level data, having at least one input subsystem signal marker, collecting at least one output subsystem level data, having at least one output subsystem signal marker and analyzing at least one measure of at least one of the at least one input subsystem signal marker and at least one output subsystem signal marker.

Abstract: A power reserve apparatus is disclosed. In one embodiment, the power reserve apparatus comprises a first module including a first set of battery cells and a first inter-cell balance adjustment unit configured to use passive balancing to reduce voltage variance among the first set of battery cells. The power reserve apparatus also comprises a second module including a second set of battery cells and a second inter-cell balance adjustment unit configured to use passive balancing to reduce voltage variance among the second set of battery cells. The power reserve apparatus further comprises an inter-module balance adjustment unit configured to use active balancing to reduce voltage variance among the first and second modules.

Abstract: A metrology pattern layout for a circuit structure is provided, the metrology pattern layout including a plurality of quadrants, in which quadrants a first wafer measurement pattern, a second wafer measurement pattern, a reticle registration pattern, and a reticle measurement pattern may be arranged to facilitate correlation of reticle metrology data with wafer metrology data. The reticle registration pattern may further include one or more outermost structural elements designed to protect other structural elements within the reticle measurement pattern from being modified in an optical proximity correction process. A method of optical proximity correction process is provided, in which a reticle measurement pattern may be obtained and classified to add or modify a rule set of the optical proximity correction process.