Abstract: An organic electroluminescent device containing a cathode, an anode, and one or more organic layers containing plural light emitting materials between the cathode and the anode, wherein the organic electroluminescent device is a multiple wavelength light emitting organic electroluminescent device emitting light from the plural light emitting materials, and which is designed so that light that has the shortest wavelength contains delayed fluorescent light can improve light emission efficiency of a short wavelength light and color tone and has a large degree of freedom in design and a simple structure.

Abstract: A semiconductor device and method of fabricating the same are provided. The semiconductor device includes a substrate having a trench and an etching stop layer. The etching stop layer is disposed in the substrate and surrounds the bottom surface and a portion of a sidewall of the trench.

Abstract: A display device, including a display region formed of a plurality of pixels, and a terminal region formed on an outer side of the display region, includes a terminal wiring formed in the terminal region, a pixel wiring formed in each of the plurality of pixels, an insulating film, which is formed in the terminal region on an upper layer of the terminal wiring, and is formed in the display region on an upper layer of the pixel wiring, and a preventing film formed in the terminal region on an upper layer of the insulating film. The terminal wiring is exposed in an electrical connection region of the terminal region.

Abstract: A method of manufacturing a display apparatus includes preparing a panel with a panel layer displaying images, a first protection film on a first surface of the panel layer with a first adhesion layer, and a second protection film on a second surface of the panel layer with a second adhesion layer, disposing the panel on a stage, cutting the panel on the stage along a closed-curve line to a predetermined depth extending from the second protection film to at least a portion of the first adhesion layer, and separating a first portion of the panel inside the closed-curve line from a second portion of the panel outside the closed-curve line, such that the second portion is removed simultaneously with the entire first protection film according to a first boundary by the line and a second boundary between the panel layer and the first protection film.

Abstract: A semiconductor memory device with a three-dimensional (3D) structure may include: a cell region arranged over a substrate, including a cell structure; a peripheral circuit region arranged between the substrate and the cell region; an upper wiring structure arranged over the cell region; main channel films and dummy channel films formed through the cell structure. The dummy channel films are suitable for electrically coupling the upper wiring structure.

Abstract: Some embodiments include an assembly having bitlines extending along a first direction. Semiconductor pillars are over the bitlines and are arranged in an array. The array includes columns along the first direction and rows along a second direction which crosses the first direction. Each of the semiconductor pillars extends vertically. The semiconductor pillars are over the bitlines. The semiconductor pillars are spaced from one another along the first direction by first gaps, and are spaced from one another along the second direction by second gaps. Wordlines extend along the second direction, and are elevationally above the semiconductor pillars. The wordlines are directly over the first gaps and are not directly over the semiconductor pillars. Gate electrodes are beneath the wordlines and are coupled with the wordlines. Each of the gate electrodes is within one of the second gaps. Shield lines may be within the first gaps.

Abstract: A first lead terminal, a second lead terminal provided parallel to the first lead terminal, and a tie bar connecting the first lead terminal and the second lead terminal are provided. The tie bar includes a first narrow-width section touching the first lead terminal, a second narrow-width section touching the second lead terminal, and a wide-width section having a larger width than the first narrow-width section and the second narrow-width section and connecting the first narrow-width section and the second narrow-width section. The wide-width section has a through-hole formed between the first narrow-width section and the second narrow-width section.

Abstract: A semiconductor device including: a conductor disposed on a substrate; a first contact disposed on the conductor; a second contact having a first portion disposed on the first contact and a second portion protruded away from the first portion in a direction parallel to the substrate, wherein the first and second contacts are disposed in an insulating layer; a via disposed on the insulating layer and the second portion of the second contact; and a metal line disposed on the via.

Abstract: A semiconductor device according to an embodiment includes a p-type SiC layer and a contact electrode electrically connected to the SiC layer. The contact electrode includes metal. And a region is provided in the SiC layer adjacent to the contact electrode. The region having an oxygen concentration not lower than 1×1016 cm?3 and not higher than 1×1021 cm?3.

Abstract: The present disclosure relates to a semiconductor light emitting device, comprising: a plurality of semiconductor layers that grows sequentially on a growth substrate, with the plurality of semiconductor layers including a first semiconductor layer having a first conductivity, a second semiconductor layer having a second conductivity different from the first conductivity, and an active layer interposed between the first semiconductor layer and the second semiconductor layer, generating a light with a first wavelength via electron-hole recombination; a first electrode, supplying either electrons or holes to the plurality of semiconductor layers; a second electrode, supplying, to the plurality of semiconductor layers, electrons if the holes are supplied by the first electrode, or holes if the electrons are supplied by the first electrode; a phosphor part provided over the first semiconductor layer on the side of the growth substrate, converting the light with the first wavelength generated in the active layer i

Abstract: A chemical mechanical polishing (CMP) method includes preparing a polishing pad, determining a first load to be applied to a conditioning disk during conditioning of the polishing pad and a first indentation depth at which tips of the conditioning disk are inserted into the polishing pad when the first load is applied to the conditioning disk, preparing a conditioning disk, and positioning the conditioning disk on the polishing pad and conditioning a surface of the polishing pad by using the conditioning disk while applying the first load to the conditioning disk.

Abstract: The present disclosure provides a bio-field effect transistor (BioFET) and a method of fabricating a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET device may include a substrate; a gate structure disposed on a first surface of the substrate and an interface layer formed on the second surface of the substrate. The interface layer may allow for a receptor to be placed on the interface layer to detect the presence of a biomolecule or bio-entity.

Abstract: In one embodiment, a semiconductor storage device includes a first interconnect extending in a first direction, a plurality of second interconnects extending in a second direction different from the first direction, and a plurality of first insulators provided alternately with the second interconnects. The device further includes a resistance change film provided between the first interconnect and at least one of the second interconnects and including a first metal layer or a first semiconductor layer that includes a first face provided on a first interconnect side and a second face provided on a second interconnect side, at least any of the first face and the second face having a curved plane shape.

Abstract: Disclosed is a method of forming a semiconductor device. The method includes providing a precursor having a substrate and protrusions over the substrate. The protrusions are interposed by trenches. The method further includes depositing a first dielectric layer over the protrusions and filling the trenches. The first dielectric layer has a first hardness. The method further includes treating the first dielectric layer with an oxidizer. The method further includes performing a chemical mechanical planarization (CMP) process to the first dielectric layer.

Abstract: Provided is a substrate structure including a substrate body, electrical contact pads and an insulating protection layer disposed on the substrate body, wherein the insulating protection layer has openings exposing the electrical contact pads, and at least one of the electrical contact pads has at least a concave portion filled with a filling material to prevent solder material from permeating along surfaces of the insulating protection layer and the electric contact pads, thereby eliminating the phenomenon of solder extrusion. Thus, bridging in the substrate structure can be eliminated even when the bump pitch between two adjacent electrical contact pads is small. As a result, short circuits can be prevented, and production yield can be increased.

Abstract: The invention relates to a method for manufacturing a Josephson junction comprising a step for providing a substrate, extending along a longitudinal direction, a step for depositing a superconducting layer on the substrate so that this layer extends from the substrate in a transverse direction, perpendicular to the longitudinal direction, and a step for irradiation of ions in a central area of the layer defined in the longitudinal direction, the method being characterized in that it includes, prior to the irradiation step, a step for removing a portion of the central area of the superconducting layer so as to delimit a set of areas of the superconducting layer aligned in the longitudinal direction including the central area and two lateral areas.

Abstract: In an exemplary method, a first layer is formed on a substrate. First overlay marks are formed in a first zone of the first layer. A non-transparent layer is formed on top of the first layer. At least a portion of the non-transparent layer is removed from an area above the first zone of the first layer. This provides optical access to the first overlay marks. A second layer is formed on top of the non-transparent layer. Second overlay marks are formed in a second zone of the second layer. Position information is obtained from each of the first overlay marks and the second overlay marks.

Abstract: To provide a field-effect transistor, containing: a substrate; a protective layer; a gate insulating layer formed between the substrate and the protective layer; a source electrode and a drain electrode, which are formed to be in contact with the gate insulating layer; a semiconductor layer, which is formed at least between the source electrode and the drain electrode, and is in contact with the gate insulating layer, the source electrode, and the drain electrode; and a gate electrode, which is formed at an opposite side to the side where the semiconductor layer is provided, with the gate insulating layer being between the gate electrode and the semiconductor layer, and is in contact with the gate insulating layer, wherein the protective layer contains a metal oxide composite, which contains at least Si and alkaline earth metal.

Abstract: A Metal-Insulator-Metal type capacitor structure (1) comprising a substrate (2), a first electrically insulating layer (14) placed on the substrate (2), a lower electrode (6) placed on the first insulating layer (14), a layer of structured metal (12) comprising a plurality of pores disposed on the lower electrode (6), a MIM capacitor (4) comprising a first conductive layer (18) placed on the structured metal layer (12) in contact with the lower electrode (6) and inside the pores, a dielectric layer (20) covering the first conductive layer (18), a second conductive layer (24) covering the dielectric layer (20) in contact with an upper electrode (8) placed on the MIM capacitor (4) and a second electrically insulating layer (16) placed on the upper electrode (8).

Abstract: A method for forming power semiconductor device is provided. The power semiconductor device includes a substrate having a device region and a surrounding termination region; and at least a power device formed in the device region of the substrate. The power semiconductor substrate also includes a termination structure having a plurality of semiconductor plugs formed in a first surface of the termination region of the substrate. Wherein the plurality of the semiconductor plugs are formed in a plurality of ring trenches formed in the first surface of the substrate in the termination regions, with a semiconductor plug formed in each of the plurality of ring trenches.