Abstract: First, second, fourth, and fifth impurity regions have a first conductivity type, and a third impurity region has a second conductivity type. The first to third impurity regions reach a first layer having the first conductivity type. The fourth and fifth impurity regions are provided on a second layer. First to fifth electrodes are provided on the first to fifth impurity regions, respectively. Electrical connection is established between the first and fifth electrodes, and between the third and fourth electrodes. A sixth electrode is provided on a gate insulating film covering a portion between the fourth and fifth impurity regions.

Abstract: The present invention provides semiconductor devices and methods for fabricating the same, in which superior dielectric termination of drift regions is accomplished by a plurality of intersecting trenches with intermediate semiconductor islands. Thus, a deep trench arrangement can be achieved without being restricted by the overall width of the isolation structure.

Abstract: Disclosed is a light-emitting element including a semiconductor substrate, an island structure formed on the semiconductor substrate and including at least a current confining layer and p-type and n-type semiconductor layers, a light-emitting thyristor formed in the island structure and having a pnpn structure, and a shift thyristor formed in the island structure and having a pnpn structure, wherein a groove portion having a depth such that the groove portion reaches at least the current confining layer is formed between a formation region of the shift thyristor of the island structure and a formation region of the light-emitting thyristor, and an oxidized region that is selectively oxidized from a side surface of the island structure and a side surface of the groove portion is formed in the current confining layer.

Abstract: A semiconductor device includes a main body made of a GaN-based semiconductor material, and at least one electrode structure. The electrode structure includes an ohmic contact layer that is formed on the main body, a buffer layer that is formed on the ohmic contact layer opposite to the main body, and a circuit layer that is made of a copper-based material and that is formed on the buffer layer opposite to the ohmic contact layer. The ohmic contact layer is made of a material selected from titanium, aluminum, nickel, and alloys thereof. The buffer layer is made of a material different from the material of the ohmic contact layer and selected from titanium, tungsten, titanium nitride, tungsten nitride, and combinations thereof.

Abstract: A semiconductor device includes a silicon substrate, a silicon carbide film formed on the silicon substrate, a mask member formed on a surface of the silicon carbide film, and having an opening section, single-crystal silicon carbide films each having grown epitaxially from the silicon carbide film exposed in the opening section as a base point, and covering the silicon carbide film and the mask member, and a semiconductor element formed on surfaces of the single-crystal silicon carbide films, an assembly section formed of the single-crystal silicon carbide films assembled to each other exists above the mask member, the semiconductor element has a body contact region, and the body contact region is disposed at a position overlapping the assembly section viewed from a direction perpendicular to the surface of the silicon substrate.

Abstract: A thermal diode comprising a superlyophobic surface, and a lyophilic surface separated from the superlyophobic surface defining a chamber. A liquid is disposed in the chamber, the liquid capable of phase changing during operation of the thermal diode. Methods of cooling and insulating bodies and rectifying heat transfer using the thermal diode.

Abstract: According to one embodiment, in a semiconductor light emitting device, a semiconductor laminated body is made by laminating, in order, a first semiconductor layer of a first conductivity-type, a semiconductor light emitting layer and a second semiconductor layer of a second conductivity-type. The semiconductor laminated body includes a plurality of trenches arranged in a periodical manner to penetrate through the second semiconductor layer and the semiconductor light emitting layer and reach the first semiconductor layer. An insulating film is buried into the trenches, and has transparency to light emitted from the semiconductor light emitting layer. A first electrode is electrically connected to the first semiconductor layer. A second electrode covers an upper surface of the second semiconductor layer.

Abstract: Semiconductor devices and manufacturing methods thereof are disclosed. In one embodiment, a semiconductor device includes a workpiece with a first region having a plurality of first features and a second region having a plurality of second features proximate the first region. The first region and the second region share a patterning overlap region disposed between the first region and the second region. The patterning overlap region includes a residue feature with an aspect ratio of about 4 or less.

Abstract: A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure comprises a first doped region and a second doped region. The first doped region comprises a first contact region. The first doped region and the first contact region have a first type conductivity. The second doped region comprises a second contact region. The second doped region and the second contact region have a second type conductivity opposite to the first type conductivity. The first doped region is adjacent to the second doped region.

Abstract: Transistor devices including stressors are disclosed. One such transistor device includes a channel region, a dielectric layer and a semiconductor substrate. The channel region is configured to provide a conductive channel between a source region and a drain region. In addition, the dielectric layer is below the channel region and is configured to electrically insulate the channel region. Further, the semiconductor substrate, which is below the channel region and below the dielectric layer, includes dislocation defects at a top surface of the semiconductor substrate, where the dislocation defects are collectively oriented to impose a compressive strain on the channel region such that charge carrier mobility is enhanced in the channel region.

Abstract: Provided are a light emitting device, a light emitting device package, and a light unit. The light emitting device includes a support substrate, a light emitting structure layer disposed on the support substrate, the light emitting structure layer including a first conductive type semiconductor layer, a second conductive type semiconductor layer, and an active layer disposed between the first conductive type semiconductor layer and the second conductive type semiconductor layer, an electrode electrically connected to the first conductive type semiconductor layer, and a volume layer disposed on the light emitting structure layer, the volume layer having a thickness greater than a thickness of the electrode.

Abstract: A multi-chip module (MCM) includes chip sub-modules that are fabricated as self-contained testable entities. The chip sub-modules plug into respective sockets in a frame of the MCM. Each chip sub-module may be tested before being plugged into the MCM. A chip sub-module may include an IC chip, such as a processor, mounted to an sub-module organic substrate that provides interconnects to the chip. The frame into which each chip sub-module plugs sits on a mini-card organic substrate that interconnects the chip sub-modules together. The MCM may include a downstop between the mini-card organic substrate and a system board to limit or prevent solder creep of solder connections between the mini-card organic substrate and the system board.

Abstract: Transistor devices including stressors are disclosed. One such transistor device includes a channel region, a dielectric layer and a semiconductor substrate. The channel region is configured to provide a conductive channel between a source region and a drain region. In addition, the dielectric layer is below the channel region and is configured to electrically insulate the channel region. Further, the semiconductor substrate, which is below the channel region and below the dielectric layer, includes dislocation defects at a top surface of the semiconductor substrate, where the dislocation defects are collectively oriented to impose a compressive strain on the channel region such that charge carrier mobility is enhanced in the channel region.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate having a first doping region and an overlying second doping region, wherein the first and second doping regions have a first conductivity type and wherein the second doping region has at least one first trench and at least one second trench adjacent thereto. A first epitaxial layer is disposed in the first trench and has a second conductivity type. A second epitaxial layer is disposed in the second trench and has the first conductivity type, wherein the second epitaxial layer has a doping concentration greater than that of the second doping region and less than that of the first doping region. A gate structure is disposed on the second trench. A method of fabricating a semiconductor device is also disclosed.

Abstract: When a semiconductor device having a surface provided with a flexible protective material is manufactured, the misalignment of the protective material occurs at the time of disposing the protective material or performing adhesion treatment. In the case where the terminal portion over the substrate has a length X of 5 mm or less, by providing a step layer with a thickness of 0.38 X or more and 2 mm or less over the element portion, a space is formed between a surface of the terminal portion and the protective material even though the protective material disposed over the step layer so as to cover the element portion is overlapped with the terminal portion. By using an attaching member including an elastic material with a surface hardness of 50 or more and 100 or less in this state, the protective material and the substrate may be attached to each other.

Abstract: A semiconductor device of an embodiment includes: a silicon carbide substrate including first and second principal surfaces; a first conductive-type first silicon carbide layer provided on the first principal surface of the silicon carbide substrate; a second conductive-type first silicon carbide region formed on a surface of the first silicon carbide layer; a first conductive-type second silicon carbide region formed on a surface of the first silicon carbide region; a second conductive-type third silicon carbide region formed on the surface of the first silicon carbide region; a gate insulating film continuously formed on the surfaces of the first silicon carbide layer, the first silicon carbide region, and the second silicon carbide region; a first electrode formed of silicon carbide formed on the gate insulating film; a second electrode formed on the first electrode; an interlayer insulating film for covering the first and second electrodes; a third electrode electrically connected to the second silicon ca

Abstract: The invention relates to a detachable substrate for the electronics, optics or optoelectronics industry, that includes a detachable layer resting on a buried weakened region. This substrate is remarkable in that this buried weakened region consists of a semiconductor material that is denser in the liquid state than in the solid state and that contains in places precipitates of naturally volatile impurities. The invention also relates to a process for fabricating and detaching a detachable substrate.

Abstract: Disclosed herein are various semiconductor devices with dual metal silicide regions and to various methods of making such devices. In one example, the device includes a gate electrode and a plurality of source/drain regions formed in a substrate proximate the gate electrode structure. The device further includes a first metal silicide region formed in each of the source/drain regions, wherein the first metal silicide region has an inner boundary and a second metal silicide region formed in each of the source/drain regions, wherein the second metal silicide region is positioned laterally between the inner boundary of the first metal silicide region and an edge of the gate electrode structure.

Abstract: Method form via chain and serpentine/comb test structures in kerf areas of a wafer. The via chain test structures comprise a first via chain and a second via chain in a first kerf area. The via chain test structures are formed such that geometrically shaped portions of the first via chain and geometrically shaped portions of the second via chain alternate along the length of the first kerf area. The methods perform relatively low (first) magnification testing to identify a defective geometrically shaped portion that contains a defective via structure. The methods then perform relatively high (second) magnification testing only within the defective geometrically shaped portion. The first magnification testing is performed at a lower magnification relative to the second magnification testing.

Abstract: A light emitting device may be provided that includes a conductive support member; a first conductive layer disposed on the conductive support member; a second conductive layer disposed on the first conductive layer; a light emitting structure including a second semiconductor layer formed on the second conductive layer, an active layer formed on the second semiconductor layer, a first semiconductor layer formed on the active layer and an insulation layer. The first conductive layer includes at least one via penetrating the second conductive layer, the second semiconductor layer and the active layer and projecting into a certain area of the first semiconductor layer. The first semiconductor layer includes an ohmic contact layer formed on or above the conductive via. The insulation layer is formed between the first conductive layer and the second conductive layer and is formed on the side wall of the via.