Patents Examined by Muna Techane
  • Semiconductor devices for controlling repair operations
    Patent number: 11670393
    Abstract: A semiconductor device includes a flag generation circuit configured to receive region fuse data and used fuse data which are generated from a fuse set selected based on a fuse set selection signal among from fuse sets and generate a bank resource flag to control a repair operation for a bank on which a repair operation has not been performed, based on the region fuse data and the used fuse data. The semiconductor device also includes a repair control circuit configured to control the repair operation for banks sharing the fuse sets based on the bank resource flag.
    Type: Grant
    Filed: November 12, 2021
    Date of Patent: June 6, 2023
    Assignee: SK hynix Inc.
    Inventors: Dong Beom Lee, Eun Je Kim, Hyeong Soo Jeong
  • Memory with single-ended sensing using reset-set latch
    Patent number: 11670351
    Abstract: Various implementations provide systems and methods for reading data from memory bit cells. An example implementation includes a read circuit that provides a single-ended output from a sensing stage. The single-ended output is received by a reset-set (RS) latch, which also receives a virtual bit line signal. The single-ended output and the virtual bit line signal provide complementary inputs to the RS latch, and the RS latch stores a sensed bit, and the sensed bit may be driven onto a data bus.
    Type: Grant
    Filed: November 29, 2021
    Date of Patent: June 6, 2023
    Assignee: QUALCOMM INCORPORATED
    Inventors: Arun Babu Pallerla, Anil Chowdary Kota, Changho Jung, Chulmin Jung
  • Re-programmable integrated circuit architecture and method of manufacture
    Patent number: 11670390
    Abstract: A re-programmable integrated circuit (IC) includes a plurality of non-volatile memory elements, each including a fuse portion initially configured to have either a first resistance value or a second resistance value. Re-programming circuitry includes a controllable element coupled to each fuse portion and selectively operable to cause an electrical current to flow through the fuse portion sufficient to cause that fuse portion to transition to an altered state having a resistance value greater than the first and second resistance values. Reference resistance circuitry is configurable between an initial state and a re-programmed state.
    Type: Grant
    Filed: September 28, 2021
    Date of Patent: June 6, 2023
    Assignee: Texas Instruments Incorporated
    Inventors: Michael Allen Ball, Anand Seshadri
  • Memory devices including processing elements, and memory systems including memory devices
    Patent number: 11664061
    Abstract: A memory device according to some aspects of the inventive concepts includes a memory cell array including a plurality of banks, at least one Processing Element (PE) connected to at least one bank selected from the plurality of banks, and a control logic configured to control an active operation in which wordlines included in each of the plurality of banks is activated, and configured to control a refresh operation in which at least one bank is refreshed, based on a PE enable signal configured to selectively enable the at least one PE.
    Type: Grant
    Filed: April 18, 2022
    Date of Patent: May 30, 2023
    Inventors: Youngcheon Kwon, Sanghyuk Kwon, Kyomin Sohn, Jaeyoun Youn, Haesuk Lee
  • Memory device and operation method thereof
    Patent number: 11664058
    Abstract: A memory device and an operation method thereof are provided. The operation method includes: in a first phase, selecting a global signal line, selecting a first string select line, unselecting a second string select line, selecting a first word line, and unselecting a second word line; sensing during a second phase; in a third phase, keeping voltages of the global signal line, the selected first word line and the unselected second word line, unselecting the first string select line and selecting the second string select line to switch voltages of the first and the second string select lines; and sensing during a fourth phase.
    Type: Grant
    Filed: December 29, 2021
    Date of Patent: May 30, 2023
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Han-Wen Hu, Yung-Chun Li
  • Semiconductor storage device
    Patent number: 11657874
    Abstract: According to one embodiment, a semiconductor storage device includes a first memory string including a first memory transistor, a first word line connected to a gate electrode of the first memory transistor, a source line connected to one end of the memory string, and a first connection transistor connected between the first word line and the source line.
    Type: Grant
    Filed: September 21, 2021
    Date of Patent: May 23, 2023
    Assignee: Kioxia Corporation
    Inventors: Sanad Bushnaq, Noriyasu Kumazaki, Masashi Yamaoka
  • Memory device and test method thereof
    Patent number: 11651832
    Abstract: A memory device includes: a normal cell region suitable for storing write data and outputting read data; a parity cell region suitable for storing write parity bits and outputting read parity bits; a pattern generation circuit suitable for generating test data whose value is sequentially increased, and providing the test data as the write data, in a first test mode; an error correction circuit suitable for generating the write parity bits based on the write data, correcting an error of the read data based on the read parity bits, and outputting the error-corrected data; and an output circuit suitable for compressing the error-corrected data and outputting the compressed data, wherein the output circuit is further suitable for compressing the read parity bits output from the parity cell region to output the compressed data, in the first test mode.
    Type: Grant
    Filed: January 12, 2021
    Date of Patent: May 16, 2023
    Assignee: SK hynix Inc.
    Inventors: Hong Ki Moon, Seung Woo Lee, Dong Hee Han
  • Sense amplifier mapping and control scheme for non-volatile memory
    Patent number: 11651800
    Abstract: A data storage includes a memory array including a plurality of memory cells, and peripheral circuitry disposed underneath the memory array. The peripheral circuitry includes an M-tier sense amplifier (SA) circuit including X stacks of SA latches, wherein each SA latch is respectively coupled to a bit line of a memory cell of the plurality of memory cells; and an N-tier memory cache data (XDL) circuit including Y stacks of XDL latches, wherein M is less than N, and X is greater than Y. The peripheral circuitry further includes data path circuitry coupling (i) each SA latch of the X stacks of SA latches to (ii) a respective XDL latch of the Y stacks of XDL latches.
    Type: Grant
    Filed: June 22, 2021
    Date of Patent: May 16, 2023
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Feng Lu, Jongyeon Kim, Ohwon Kwon
  • Page buffer circuit and memory device including the same
    Patent number: 11646064
    Abstract: Provided are a page buffer and a memory device including the same. A memory device includes: a memory cell array including a plurality of memory cells; and a page buffer circuit including page buffer units in a first horizontal direction, the page buffer units being connected to the memory cells via bit lines, and cache latches in the first horizontal direction, the cache latches corresponding to the page buffer units, wherein each of the page buffer units includes one or more pass transistors connected to a sensing node of each of the plurality of page buffer units, the sensing node electrically connected to a corresponding bit line. Each sensing node included in each of the page buffer units and the combined sensing node are electrically connected to each other through the pass transistors.
    Type: Grant
    Filed: March 19, 2021
    Date of Patent: May 9, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yongsung Cho, Inho Kang, Taehyo Kim, Jeunghwan Park, Jinwoo Park
  • Memory controller and related memory
    Patent number: 11646066
    Abstract: A memory controller includes a command processor. When an access command is performed by the memory controller, the command processor generates a row address information to the memory before issuing an active command to the memory. The row address information and the active command are issued by the command processor based on the access command.
    Type: Grant
    Filed: November 23, 2020
    Date of Patent: May 9, 2023
    Assignee: Etron Technology, Inc.
    Inventor: Chun Shiah
  • Data storage device and operating method thereof
    Patent number: 11646067
    Abstract: A data storage device includes a nonvolatile memory device and a controller including a command parser configured to match a clock corresponding to each of a plurality of memory access types to generate a clock index matched with each of the memory access types and configured to determine, when a command is received, a memory access type of the command and the clock index matched with the determined memory access type by analyzing the command, and a memory interface configured to determine a locking value and the clock index corresponding to each of a plurality of clocks having different frequencies and change the locking value for processing of a command according to the clock index determined by the command parser.
    Type: Grant
    Filed: August 20, 2021
    Date of Patent: May 9, 2023
    Assignee: SK hynix Inc.
    Inventor: Dae Geun Jee
  • Method and system for enhanced multi-address read operations in low pin count interfaces
    Patent number: 11631441
    Abstract: A memory device supporting multi-address read operations improves throughput on a bi-directional serial port. The device includes a memory array and an input/output port having an input mode and an output mode. The input/output port has at least one signal line used alternately in both the input and output modes. A controller includes logic configured to execute a multi-address read operation in response to receiving a read command on the input/output port, the multi-address read operation including receiving a first address and a second address using the at least one signal line before outputting data.
    Type: Grant
    Filed: March 22, 2022
    Date of Patent: April 18, 2023
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Kuen-Long Chang, Su-Chueh Lo, Yung-Feng Lin
  • Non-volatile memory device, programming method thereof, and storage device having the same
    Patent number: 11626171
    Abstract: A method of programming a nonvolatile memory device includes performing a single-pulse program operation in a program loop, determining whether a condition is satisfied in the a program loop, and performing a multi-pulse program operation in a next program loop when the condition is satisfied. The single-pulse program operation includes applying a first program pulse and applying plural verification pulses, the multi-pulse program operation includes applying a second program pulse, applying a third program pulse, and applying plural verification pulses, and each of the second program pulse and the third program pulse has a level lower than a level of the first program pulse.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: April 11, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Joonsuc Jang, Hyunggon Kim, Sangbum Yun, Dongwook Kim, Kyungsoo Park, Sejin Baek
  • Semiconductor memory devices, memory systems, and methods of operating semiconductor memory devices
    Patent number: 11626185
    Abstract: A method includes replacing an address of a first normal memory cell in a first column of a first memory block with a destination address that is an address of a second normal memory cell in a second column of the first memory block, and reassigning the address of the second normal memory cell in the second column of the first memory block to an address of a first redundancy memory cell in a redundancy block of the memory device.
    Type: Grant
    Filed: April 18, 2022
    Date of Patent: April 11, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyung-Ryun Kim, Yoon-Na Oh, Hyung-Jin Kim, Hui-Kap Yang, Jang-Woo Ryu
  • Anti-fuse sensing device and operation method thereof
    Patent number: 11626177
    Abstract: An anti-fuse sensing device and an operation method thereof are provided. The anti-fuse sensing device is adapted for sensing a resistance state of an anti-fuse. The anti-fuse sensing device includes a voltage generating circuit, a comparison circuit, and a sensing circuit. The voltage generating circuit is configured to generate a comparison voltage that changes with temperature. The comparison circuit is coupled to the voltage generating circuit to receive the comparison voltage. The comparison circuit is configured to compare the comparison voltage with a reference voltage, and convert a difference between the comparison voltage and the reference voltage into a bias voltage that changes with temperature. The sensing circuit is coupled to the comparison circuit to receive the bias voltage. The sensing circuit is configured to sense the resistance state of the anti-fuse according to the bias voltage.
    Type: Grant
    Filed: December 23, 2021
    Date of Patent: April 11, 2023
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Chih-Hang Chang
  • Memory readout circuit and method
    Patent number: 11615860
    Abstract: A circuit includes an array of OTP cells, an array of NVM cells, an amplifier coupled to each of the array of OTP cells and the array of NVM cells, and a control circuit configured to generate one or more control signals. Responsive to the one or more control signals, the amplifier is configured to generate an output voltage based on a current received from the array of OTP cells in a first configuration, and generate the output voltage based on a voltage received from the array of NVM cells in a second configuration.
    Type: Grant
    Filed: February 14, 2022
    Date of Patent: March 28, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Chih-Min Liu
  • Merged command decoder for half-frequency circuits of a memory device
    Patent number: 11605408
    Abstract: A memory device includes a command interface configured to receive a command from a host device via multiple command address bits. The memory device also includes a merged command decoder configured to receive the command and to determine whether the command matches a bit pattern corresponding to multiple command types. The merged command decoder is also configured to, in response to the command matching the bit pattern, asserting a latch signal. The memory device also includes a latch configured to capture the multiple command address bits based at least in part on assertion of the latch signal.
    Type: Grant
    Filed: November 3, 2021
    Date of Patent: March 14, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Navya Sri Sreeram, Kallol Mazumder
  • Memory system and delay control method
    Patent number: 11605407
    Abstract: According to one embodiment, a memory system includes a memory interface circuit. The memory interface circuit has delay circuits, a detection circuit, and a control circuit. One of the delay circuits applies a delay to a data signal. Another delay circuit generates, fora strobe signal, a first delay strobe signal, a second delay strobe signal, and a third delay strobe signal, each with different delay amounts. The detection circuit detects a drift in the timing of the first delay strobe signal with respect to the delayed data signal by using the delay data signal, the first delay strobe signal, the second delay strobe signal, and the third delay strobe signal. The control circuit adjusts the first delay amount, the second delay amount, and the third delay amount in a direction to compensate the drift.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: March 14, 2023
    Assignee: Kioxia Corporation
    Inventor: Shuichi Takada
  • Counter-based read in memory device
    Patent number: 11594297
    Abstract: Methods and apparatuses with counter-based reading are described. A memory cells of a codeword are accessed and respective voltages are generated. A reference voltage is generated and a logic state of each memory cell is determined based on the reference voltage and the respective generated cell voltage. The reference voltage is modified until a count of memory cells determined to be in a predefined logic state with respect to the last modified reference voltage value meets a criterium. In some embodiments the criterium may be an exact match between the memory cells count and an expected number of memory cells in the predefined logic state. In other embodiments, an error correction (ECC) algorithm may be applied while the difference between the count of cells in the predefined logic state and the expected number of cells in that state does not exceed a detection or correction power of the ECC.
    Type: Grant
    Filed: February 1, 2022
    Date of Patent: February 28, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Umberto Di Vincenzo, Riccardo Muzzetto, Ferdinando Bedeschi
  • Content addressable memory device having electrically floating body transistor
    Patent number: 11594280
    Abstract: A content addressable memory cell includes a first floating body transistor and a second floating body transistor. The first floating body transistor and the second floating body transistor are electrically connected in series through a common node. The first floating body transistor and the second floating body transistor store complementary data.
    Type: Grant
    Filed: August 1, 2021
    Date of Patent: February 28, 2023
    Assignee: Zeno Semiconductor, Inc.
    Inventors: Benjamin S. Louie, Jin-Woo Han, Yuniarto Widjaja