Abstract: A semiconductor light-emitting device fabricated in a nitride material system has an active region disposed over a substrate. The active region comprises a first aluminium-containing layer forming the lowermost layer of the active region, a second aluminium-containing layer forming the uppermost layer of the active region, and at least one InGaN quantum well layer disposed between the first aluminium-containing layer and the second aluminum-containing layer. The aluminium-containing layers provide improved carrier confinement in the active region, and so increase the output optical power of the device.

Abstract: There is disclosed a semiconductor device comprising at least one semiconductor element, one chip mounting base being provided at least one first interconnection on one major surface thereof and at least one second interconnection on the other major surface thereof, and the semiconductor element being electrically connected to at least the one first interconnection and mounted on the one major surface, a sealing member being provided on the one major surface of the chip mounting base and covering the semiconductor element and the first interconnection, at least one third interconnection being provided on a surface of the sealing member, and at least one fourth interconnection being provided in the sealing member and the chip mounting base, and electrically connected to the first interconnection, the second interconnection, and the third interconnection.

Abstract: A vertical JFET 1a according to the present invention has an n+ type drain semiconductor portion 2, an n-type drift semiconductor portion 3, a p+ type gate semiconductor portion 4, an n-type channel semiconductor portion 5, an n+ type source semiconductor portion 7, and a p+ type gate semiconductor portion 8. The n-type drift semiconductor portion 3 is placed on a principal surface of the n+ type drain semiconductor portion 2 and has first to fourth regions 3a to 3d extending in a direction intersecting with the principal surface. The p+ type gate semiconductor portion 4 is placed on the first to third regions 3a to 3c of the n-type drift semiconductor portion 3. The n-type channel semiconductor portion 5 is placed along the p+ type gate semiconductor portion 4 and is electrically connected to the fourth region 3d of the n-type drift semiconductor portion 3.

Abstract: A method and structure for an integrated circuit comprising a substrate of a first polarity, a merged triple well region of a second polarity and a doped region of the second polarity abutting the well region. The doped region is adapted to suppress latch-up in the integrated circuit. The doped region is placed under semiconductor devices of the first polarity and under the well region contact region. Additionally, the structure may further include a deep trench (DT) structure and trench isolation (TI) structure to further improve latchup robustness.

Abstract: The present invention relates to a MOS transistor which is capable of compensating the shortcomings of the conventional MOS transistor having three gate electrodes. In order to achieve the object the MOS transistor of the present invention is characterized in that the sidewall gates are made of material having an energy band gap higher than that of the material constituting the main gate or the sidewall gates are implanted with holes (or positive charges) or electrons (or negative charges).

Abstract: Non-volatile field effect devices and circuits using same. A non-volatile field effect device includes a source, drain and gate with a field-modulatable channel between the source and drain. Each of the source, drain, and gate have a corresponding terminal. An electromechanically-deflectable, nanotube switching element is electrically positioned between one of the source, drain and gate and its corresponding terminal. The others of the source, drain and gate are directly connected to their corresponding terminals. The nanotube switching element is electromechanically-deflectable in response to electrical stimulation at two control terminals to create one of a non-volatile open and non-volatile closed electrical communication state between the one of the source, drain and gate and its corresponding terminal. Under one embodiment, one of the two control terminals has a dielectric surface for contact with the nanotube switching element when creating a non-volatile open state.

Abstract: A semiconductor device structure includes a gate structure disposed on a portion of substrate, source and drain regions disposed adjacent to the portion so as to form a channel region in the portion, and trench isolation regions located immediately adjacent to the source and drain regions. At least portions of the trench isolation regions include stress materials such that the materials generate shear stresses in the channel region.

Abstract: A light emitting device includes an n-type semiconductor layer, an active layer for generating light, the active layer being in electrical contact with the n-type semiconductor layer. A p-type semiconductor layer is in electrical contact with the active layer, and a p-electrode is in electrical contact with the p-type semiconductor layer. The p-electrode includes a layer of silver. In a preferred embodiment of the present invention, the n-type semiconductor layer and the p-type semiconductor layer are constructed from group III nitride semiconducting materials. In one embodiment of the invention, the silver layer is sufficiently thin to be transparent. In other embodiments, the silver layer is thick enough to reflect most of the light incident thereon. A fixation layer may be provided. The fixation layer may be a dielectric or a conductor.

Abstract: According to an aspect of the invention, a structure is provided in which an array of trench capacitors includes a well contact to a merged buried plate diffusion region. The array, which is disposed in a substrate, includes a contact for receiving a reference potential. Each trench capacitor includes a node dielectric and a node conductor formed within the trench. Buried plate (BP) diffusions extend laterally outward from a lower portion of each trench of the array, the BP diffusions merging to form an at least substantially continuous BP diffusion region across the array. An isolation region extends over a portion of the BP diffusion region. A doped well region is formed within the substrate extending from a major surface of the substrate to a depth below a top level of the substantially continuous BP diffusion region. An electrical interconnection is also provided to the well region.

Abstract: Nanoelectromechanical switch systems (NEMSS) that are structured around the mechanical manipulation of nanotubes are provided. Such NEMSS can realize the functionality of, for example, automatic switches, adjustable diodes, amplifiers, inverters, variable resistors, pulse position modulators (PPMs), and transistors. In one embodiment, a nanotube is anchored at one end to a base member. The nanotube is also coupled to a voltage source. This voltage source creates an electric charge at the tip of the free-moving-end of the nanotube that is representative of the polarity and intensity of the voltage source. The free-moving end of this nanotube can be electrically controlled by applying an electric charge to a nearby charge member layer that is either of the same (repelling) or opposite (attracting) polarity of the nanotube.

Abstract: An image sensor cell includes a first MOS transistor coupled to an operating voltage for providing an output voltage of the image sensor cell with the output voltage changing conformingly with a voltage on a gate of the first MOS transistor. A photodiode is coupled to a floating node which further controls the voltage of the gate of the first MOS transistor. A photoconductor is coupled between the operating voltage and the floating node. The photoconductor has its resistance varying in response to a magnitude change of an imposed illumination so that the floating node is provided with additional electrical charges conformingly through the photoconductor while the photodiode drains electrical charges, thereby decreasing a voltage reduction rate of the voltage on the gate of the first MOS transistor.

Abstract: A light receiving panel provided with a plurality of particulate semiconductor elements (solar cells) or a light emitting panel provided with a plurality of particulate semiconductor elements (light emitting diodes) is disclosed. In the solar cell panel, a printed wiring sheet is constructed by forming printed wiring and retaining holes in the form of a matrix with a plurality of rows and a plurality of columns in a printed wiring sheet material made of a thin transparent synthetic resin; a plurality of solar cells are respectively mounted in the plurality of retaining holes, these cells are resin-sealed by a transparent synthetic resin material, a positive pole terminal and negative pole terminal exposed to the outside are formed, and a plurality of solar cell panels are constructed so that series connection, parallel connection or series-parallel connection is possible.

Abstract: Extended-drain MOS transistor devices and fabrication methods are provided, in which a drift region of a first conductivity type is formed between a drain of the first conductivity type and a channel. The drift region comprises first and second portions, the first portion extending partially under a gate structure between the channel and the second portion, and the second portion extending laterally between the first portion and the drain, wherein the first portion of the drift region has a concentration of first type dopants higher than the second portion.

Abstract: An electronic apparatus comprising one or more microstructures on a substrate and a method for fabricating the electronic apparatus. The microstructures have alignment structures that allow the microstructures to be oriented in receptacles having shapes that are complementary to the shapes of the alignment structures. The alignment structures are shapes that vary when rotated 360°, such that the microstructures are positioned at a specific orientation in the receptacles.

Abstract: A light-receiving device incorporating particulate semiconductor devices (solar cells) having a light-to-electricity transducing function or a light-emitting device incorporating particulate semiconductor devices (light-emitting diodes) having an electricity-to-light transducing function. In a solar cell panel shown, solar cells are arrayed on the same plane in rows. Each row of solar cells are parallel interconnected through positive electrode wires and negative electrode wires, and solar cells of adjoining rows are interconnected in series through a connection part. These solar cells connected in parallel and in series are covered with a transparent covering member, thus forming a panel. These solar cells each have externally exposed positive and negative electrode terminals, and therefore the solar cells can be interconnected in parallel, in series, or in parallel and series. When the conductive wires and the covering member are flexible, the device can be deformable.

Abstract: A semiconductor package comprising a plurality of elongate leads which each have opposed inner and outer ends, opposed first and second surfaces, and a third surface which is disposed in opposed relation to the first surface and recessed relative to the second surface. The second surface of each lead is positioned in close proximity to the inner end thereof. The third surface of each lead extends to the outer end thereof. A semiconductor die is attached to portions of the first surfaces of at least some of the leads. The semiconductor die is itself electrically connected to at least some of the leads. A package body covers the semiconductor die and the leads such that the second surfaces of the leads are exposed in a bottom surface of the package body and the outer ends of the leads are exposed in respective side surfaces of the package body.

Abstract: A method of forming a dielectric film composed of metal oxide under an atmosphere of activated vapor containing oxygen. In the method of forming the dielectric film, a metal oxide film is formed on a semiconductor substrate using a metal organic precursor and O2 gas while the semiconductor substrate is exposed under activated vapor atmosphere containing oxygen, and then, the metal oxide film is annealed while the semiconductor substrate is exposed under activated vapor containing oxygen. The annealing may take place in situ with the formation of the metal oxide film, at the same or substantially the same temperature as the metal oxide forming, and/or at least one of a different pressure, oxygen concentration, or oxygen flow rate as the metal oxide forming.

Abstract: In a semiconductor device of the present invention, the top surface of an n-type silicon carbide layer formed on a silicon carbide substrate is miscut from the (0001) plane in the <11-20> direction. A gate electrode, a source electrode and other elements are arranged such that in a channel region, the dominating current flows along a miscut direction. In the present invention, a gate insulating film is formed and then heat treatment is performed in an atmosphere containing a group-V element. In this way, the interface state density at the interface between the silicon carbide layer and the gate insulating film is reduced. As a result, the electron mobility becomes higher in a miscut direction A than in the direction perpendicular to the miscut direction A.

Abstract: A transistor and a semiconductor integrated circuit with a reduced layout area. Area reduction of a transistor is realized by arranging contacts at higher density. Specifically, in a transistor including a pair of impurity regions and a gate electrode 604 sandwiched therebetween, one of the impurity regions has respective contact holes (a first contact hole 601 and a second contact hole 602) and the other impurity region has a contact hole (a third contact hole 603), and contacts of the contact holes 601 to 603 or regions 605 to 607 each including a margin for a contact are arranged so as to be a triangular lattice except for the gate electrode 604.

Abstract: In one embodiment of the invention, an integrated circuit package includes an integrated circuit, a package substrate, a first bump, a second bump and a shunt to provide for current distribution and reliability redundancy. The first and second bumps provide a first and second electric current pathway between the integrated circuit and package substrate. The shunt provides a third electric current pathway between the first bump and the second bump.