Abstract: Apparatus for synchronizing a clock signal to a pulse comprises a clock signal generator (1) for generating a first clock signal having a frequency equal to that of a desired clock signal. A delay circuit (2) to which the first clock signal is fed generates a number of time delayed versions of the first clock signal, each time delay being less than the period of the first clock signals. Logic (9) compares the time delayed versions of the first clock signal and the original clock signal at the time of occurrence of the pulse and selects as the desired clock signal, a version of the first clock signal which has changed state close to the time of occurence of the pulse.

Abstract: A relay-less load driver circuit includes an FET that couples a battery to a load. A bias circuit that selectively turns the FET on during normal operation also turns the FET on in reverse-battery conditions to avoid high power dissipation by an intrinsic diode associated with the FET.