Abstract: A technique to control write operations in a logical partition. For example, a device can receive a user specified write threshold for the logical partition that is hosted on a pool of memory cells shared by a plurality of logical partitions in wear leveling. An accumulated amount of data written into the memory cells according to write requests addressing the logical partition is tracked. In response to the accumulated amount reaches the write threshold, further write requests addressing the logical partition can be blocked, rejected, and/or ignored. For example, the logical partition can be used to buffer data for time shift in playing back content streaming from a server. Write operations for time shift can be limited via the user specified threshold to prevent overuse of the total program erasure budget of the pool of memory cells shared with other logical partitions.

Abstract: A computing device may determine a respective disk access usage of flash memory of the computing device by each of a plurality of applications. The computing device may compare the respective disk access usage of the flash memory by each of the plurality of applications with a respective application-specific disk access overuse threshold to determine disk access overuse of the flash memory by an application of the plurality of applications. The computing device may, in response to determining the disk access overuse of the flash memory by the application, terminate the application.

Abstract: The present disclosure generally relates to reducing exit latency when transitioning from non-operational power states. Before entering a non-operational power state, specific data in databases and/or tables can be identified as being recently utilized by the host device. In addition to saving the databases and/or tables, a recovery code is also stored to identify that specific data. Upon transitioning back to an operational power state, the recovery code is detected and the specific data can be recovered rather than recovering the entire database and/or table. Data not identified in the recovery code need not be recovered from always-on memory. In so doing, when transitioning back to an operational power state, the latency will be reduced compared to a situation where all data is stored in always-on memory.

Abstract: The present disclosure generally relates to more efficient use of a delta buffer. To utilize the delta buffer, an efficiency can be gained by utilizing absolute delta entries and relative delta entries. The absolute delta entry will include the type of delta entry, the L2P table index, the L2P table offset, and the PBA. The relative delta entry will include the type of delta entry, the L2P table offset, and the PBA offset. The relative delta entry will utilize about half of the storage space of the absolute delta entry. The relative delta entry can be used after an absolute delta entry so long as the relative delta entry is for data stored in the same block as the previous delta entry. If data is stored in a different block, then the delta entry will be an absolute delta entry.

Abstract: The present disclosure generally relates to more efficient use of a delta buffer. To Utilize the delta buffer, an efficiency can be gained by utilizing absolute delta entries and relative delta entries. The absolute delta entry will include the type of delta entry, the L2P table index, the L2P table offset, and the PBA. The relative delta entry will include the type of delta entry, the L2P table offset, and the PBA offset. The relative delta entry will utilize about half of the storage space of the absolute delta entry. The relative delta entry can be used after an absolute delta entry so long as the relative delta entry is for data stored in the same block as the previous delta entry. If data is stored in a different block, then the delta entry will be an absolute delta entry.

Abstract: Provided is a method of controlling a RAID controller, the method including generating, by the RAID controller, a command sequence, and transmitting, by the RAID controller, when a first cache barrier command included in the command sequence is identified, at least one cache barrier command to an arbitrary disk constituting a RAID before transmitting a first write command arranged after the first cache barrier command in the command sequence to the arbitrary disk.

Abstract: A coherency manager for receiving snoop requests addressed in a physical address space, the snoop requests relating to a cache memory addressable using a virtual address space, the cache memory having a plurality of coherent cachelines, the coherency manager comprising: a reverse translation module configured to maintain a mapping from physical addresses to virtual addresses for each coherent cacheline held in the cache memory; and a snoop processor configured to: receive a snoop request relating to a physical address; in response to the received snoop request, determine whether the physical address is mapped to a virtual address in the reverse translation module; and process the snoop request in dependence on that determination.

Abstract: Storage devices are described herein that are capable of communicating with host-computing devices using multiple protocols. These Multi-Protocol Storage Devices (MPSDs) can be configured to utilize a persistent memory region (PMR) across a variety of protocols. Often, one of these protocols is the Non-Volatile Memory express (NVMe) protocol which provides for the ability to utilize and manage a PMR within the storage device. Other protocols may not have native support for PMR like the NVMe protocol does. Therefore, MPSDs are disclosed that may determine which protocol is in use in response to an initialization event and adjust the use of the PMR as needed based on the determined protocol. These adjustments may allow for the direct access of the PMR as an extension of general memory storage or may be configured to provide increased performance of the storage device overall. These storage devices may be hot-swappable between numerous host-computing systems.

Abstract: A memory image can be captured by generating metadata indicative of a state of volatile memory and/or byte-addressable PMEM at a particular time during execution of a process by an application. This memory image can be persisted without copying the in-memory data into a separate persistent storage by storing the metadata and safekeeping the in-memory data in the volatile memory and/or PMEM. Metadata associated with multiple time-evolved memory images captured can be stored and managed using a linked index scheme. A linked index scheme can be configured in various ways including a full index and a difference-only index. The memory images can be used for various purposes including suspending and later resuming execution of the application process, restoring a failed application to a previous point in time, cloning an application, and recovering an application process to a most recent state in an application log.

Abstract: A data storage device comprises a plurality of storage elements, each storage element configured for storing a piece of information. The plurality of storage elements is accessible as a plurality of word sets, each word set comprising a set of storage elements, and is accessible as a plurality of slice sets, each slice set comprising a set of storage elements. Each storage element is a part of a word set and a part of a slice set. The device further comprises a control unit configured for obtaining word information and slice information and for executing a write operation to parallelly write the word information into a first word set of the plurality of word sets and the slice information into a first slice set of the plurality of slice sets, wherein the first word set and the first slice set comprise a common storage element defined by an overlap of the first word set and the first slice set in a layout of the plurality of storage elements.

Abstract: This application relates to a data transmission circuit, a method, and a storage device. The data transmission circuit includes a delay module and a mode register data processing unit. The delay module delays a first preset time when receiving a mode register read command, and generates delayed read command. The mode register data processing unit is connected to the delay module, and reads setting parameters from the mode register in response to the mode register read command, and outputs the setting parameters in response to the delayed read command.

Abstract: A method, computer program product, and computer system for exposing, by a user block layer of a computing device, a storage device as a block device to an application associated with an IO request. A Non-Volatile Memory Express (NVMe) protocol layer of the computing device may expose a NVMe storage device associated with the IO request to the user block layer. A NVMe-over-RDMA layer of the computing device may create a NVMe RDMA queue for the IO request to be processed.

Abstract: A method of writing to a tiered memory system of a computing device, the tiered memory system including volatile memory and persistent memory (PMEM), includes the steps of: in response to a first write request including first data to write to a first page of the tiered memory system, copying contents of the first page to a second page located in the PMEM; after copying the contents of the first page to the second page, writing the first data to the second page; and after writing the first data to the second page, updating a first mapping of the tiered memory system to reference the second page instead of the first page.

Abstract: A method includes receiving, by a device, of a control signal identifying a first application from among a plurality of compressed applications stored in a non-volatile memory of the device. The first application is stored in a first location of the non-volatile memory. The device decompresses the first application. The decompressing includes storing the decompressed first application into the non-volatile memory at least partially into the first location, and into a second location storing a second compressed application among the plurality of applications. The decompressed first application overwriting at least a portion of the second compressed application. The method may be performed as part of a customization process of an integrated circuit including the non-volatile memory.

Abstract: A storage system supports several memory mappings that translate data bits into different physical voltage levels in its non-volatile memory. The storage system receives a selection of one of the memory mappings from a host, which makes the selection based on an application or expected workload of the host. The storage system uses the selected memory mapping for a memory access operation, such as a read operation or a write operation.

Abstract: Disclosed are techniques that provide for deduplication in an efficient and effective manner. For example, such methods, computer program products, and computer systems can include generating new feature information for one or more portions of a new backup image, generating first container range information by performing a container range calculation using the new feature information, generating existing feature information for one or more portions of an existing backup image, generating second container range information by performing the container range calculation using the existing feature information, determining a container range affinity between the first container range information and the second container range information, identifying at least one portion of the one or more portions of the existing backup image using a result of the determining, and prefetching the one or more fingerprints corresponding to the at least one portion of the one or more portions of the existing backup image.

Abstract: A memory management method of a storage device including: programming write-requested data in a memory block; counting an elapse time from a time when a last page of the memory block was programmed with the write-requested data; triggering a garbage collection of the storage device when the elapse time exceeds a threshold value; and programming valid data collected by the garbage collection at a first clean page of the memory block.

Abstract: A volume to which a storage function is applied is migrated without copying data written to a volume as a migration object between computers while maintaining functionality of the storage function. A plurality of computers are accessibly connected to each of one or more physical storage devices. Each computer migrates ownership of the volume as the migration object to a computer as a destination. When the migration object volume from a first computer to a second computer is an owner volume to which a storage function is applied, the storage function requiring control data for I/O of data, the control data being metadata other than domain mapping data (indicating a relationship between a volume region and a storage region and being metadata for the owner volume), in place of or in addition to the domain mapping data.

Abstract: A cache system, having: a first cache; a second cache; a configurable data bit; and a logic circuit coupled to a processor to control the caches based on the configurable bit. When the configurable bit is in a first state, the logic circuit is configured to: implement commands for accessing a memory system via the first cache, when an execution type is a first type; and implement commands for accessing the memory system via the second cache, when the execution type is a second type. When the configurable data bit is in a second state, the logic circuit is configured to: implement commands for accessing the memory system via the second cache, when the execution type is the first type; and implement commands for accessing the memory system via the first cache, when the execution type is the second type.

Abstract: A system, method, and device for providing information between a parent node and a child node is disclosed. The method includes issuing, by a parent node to a child node, an identifier and a set of storage locations, the identifier and the set of storage locations being issued in connection with the parent node instructing the child node to perform an operation, determining, by the parent node, whether a response pertaining to the operation has been received from the child node within a predetermined period of time, in response to a determination that the parent node has not received the response from the child node within the predefined period of time, checking the set of storage locations for a response associated with the identifier.