Patents Examined by Nanci N Wong
  • Patent number: 11847352
    Abstract: A system, method, and device for providing information between a parent node and a child node is disclosed. The method includes issuing, by a parent node to a child node, an identifier and a set of storage locations, the identifier and the set of storage locations being issued in connection with the parent node instructing the child node to perform an operation, determining, by the parent node, whether a response pertaining to the operation has been received from the child node within a predetermined period of time, in response to a determination that the parent node has not received the response from the child node within the predefined period of time, checking the set of storage locations for a response associated with the identifier.
    Type: Grant
    Filed: January 25, 2022
    Date of Patent: December 19, 2023
    Assignee: Ridgeline, Inc.
    Inventors: Timophey Zaitsev, Hayden Ray Hudgins
  • Patent number: 11836074
    Abstract: Methods, systems, and devices for multiple flash translation layers (FTLs) at a memory device are described to support two or more FTLs within a memory device. A first FTL may be configured to support data mapping using a defined granularity and a second FTL may be configured to support data mapping using a smaller granularity than the defined granularity or data that does not match the defined granularity, based on one or more characteristics of the data. A memory device may select between the FTLs to map data based on the one or more characteristics of the data and may write the data to the memory device. The memory device may store logical-to-physical mapping associated with the data, among other information, using the selected FTL.
    Type: Grant
    Filed: October 7, 2020
    Date of Patent: December 5, 2023
    Assignee: Micron Technology, Inc.
    Inventor: David A. Palmer
  • Patent number: 11816041
    Abstract: Various examples are directed to systems and methods for programming memory. A programming appliance may receive a command file comprising a first pre-generated digital signature. The first pre-generated digital signature may be associated with a memory system, with a first command and with a first memory system counter value. The programming appliance may send to a memory system a first command message. The first command system may comprise the first command and the first pre-generated digital signature.
    Type: Grant
    Filed: August 15, 2022
    Date of Patent: November 14, 2023
    Assignee: Micron Technology, Inc.
    Inventor: Olivier Duval
  • Patent number: 11816029
    Abstract: A system, method, and machine-readable storage medium for performing garbage collection in a distributed storage system are provided. In some embodiments, an efficiency level of a garbage collection process is monitored. The garbage collection process may include removal of one or more data blocks of a set of data blocks that is referenced by a set of content identifiers. The set of slice services and the set of data blocks may reside in a cluster, and a set of probabilistic filters (e.g., Bloom filters) may indicate whether the set of data blocks is in-use. At least one parameter of a probabilistic filter of the set of probabilistic filters may be adjusted (e.g., increased or reduced) if the efficiency level is below the efficiency threshold. Garbage collection may be performed on the set of data blocks in accordance with the set of probabilistic filters.
    Type: Grant
    Filed: March 10, 2022
    Date of Patent: November 14, 2023
    Assignee: NetApp, Inc.
    Inventors: Alyssa Proulx, Wei Sun
  • Patent number: 11809707
    Abstract: A plurality of computing devices are communicatively coupled to each other via a network, and each of the plurality of computing devices is operably coupled to one or more of a plurality of storage devices. A plurality of failure resilient address spaces are distributed across the plurality of storage devices such that each of the plurality of failure resilient address spaces spans a plurality of the storage devices. The plurality of computing devices maintains metadata that maps each failure resilient address space to one of the plurality of computing devices. Each of the plurality of computing devices is operable to read from and write to a plurality of memory blocks, while maintaining an extent in metadata that maps the plurality of memory blocks to the failure resilient address space.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: November 7, 2023
    Inventors: Maor Ben Dayan, Omri Palmon, Liran Zvibel, Kanael Arditti
  • Patent number: 11809328
    Abstract: The present invention provides a control method of the flash memory controller. In the control method, by establishing a valid page count table, a detailed valid page count table and/or a zone valid page count table according to deallocate command from the host device, the flash memory controller can efficiently and quickly determine if any one of the zones does not have any valid data, so that the flash memory controller can recommend the host device to send a reset command to reset the zone. In addition, after receiving the reset command from the host device, the flash memory controller can use a garbage collection operation or directly put the blocks corresponding to the erased zone into a spare block pool, for the further use.
    Type: Grant
    Filed: January 24, 2022
    Date of Patent: November 7, 2023
    Assignee: Silicon Motion, Inc.
    Inventors: Ken-Fu Hsu, Ching-Hui Lin
  • Patent number: 11797397
    Abstract: In one example, a method for writing data includes receiving a write request and performing a first type of logging process in connection with the write request, and creating a corresponding first logging record. Additionally, a second type of logging process is performed in connection with the write request, and a corresponding second logging record created, where the second type of logging process is different from the first type of logging process. Next, a determination is made, as between the two logging records, which of the logging records requires the least amount of non-volatile random access memory (NVRAM), and the logging record that requires the least amount of NVRAM is written to the NVRAM.
    Type: Grant
    Filed: October 28, 2021
    Date of Patent: October 24, 2023
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Pengju Shang, George Mathew, Dhawal Bhagwat, Pranay Singh, Englin Koay
  • Patent number: 11797219
    Abstract: A storage device, a server device including the storage device and a method of operating the storage device are provided. The storage device includes a nonvolatile memory configured to store first control information related to a memory operation performed in a first temperature range and second control information related to a memory operation performed in a second temperature range different from the first temperature range, the first control information and the second control information being stored separately from each other, and a storage controller configured to receive a temperature sensed from a temperature sensor, determine a target temperature by processing the sensed temperature, select one of the first control information and the second control information based on the determined target temperature, and perform a memory operation on the nonvolatile memory using the selected control information.
    Type: Grant
    Filed: June 10, 2021
    Date of Patent: October 24, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young-Seop Shim, Kyung Duk Lee, Chan Moo Park, In Kap Chang, Jong-Sung Na
  • Patent number: 11755208
    Abstract: Recurrent Neural Networks (RNNs) wherein a non-volatile memory (NVM) array provides a memory bank for the RNN. The RNN may include a Neural Turning Machine (NTM) and the memory bank may be an NTM matrix stored in the NVM array. In some examples, a data storage device (DSD) that controls the NVM array includes both a data storage controller and a separate NTM controller. The separate NTM controller accesses the NTM matrix of the NVM array directly while bypassing flash translation layer (FTL) components of the data storage controller. Additionally, various majority wins error detection and correction procedures are described, as well as various disparity count-based procedures.
    Type: Grant
    Filed: October 12, 2021
    Date of Patent: September 12, 2023
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Ariel Navon, Alexander Bazarsky, Ofir Pele, Daniel Joseph Linnen
  • Patent number: 11747994
    Abstract: A system can include multiple memory devices and a processing device that is operatively coupled with the memory devices as well as with a controller device, and a sequencer device, where the controller device is configured to perform operations. The operations can include, in response to receiving a potential power loss indication signal, receiving a power fault interrupt detection signal, as well as synchronizing the power fault interrupt detection signal. They can also include sending one or more memory access commands to the sequencer device. The operations can also include executing the one or more memory access commands on a medium and stopping transmission of commands based on a power loss handling setting while executing the commands.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: September 5, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Chih-Kuo Kao, Yi-Min Lin
  • Patent number: 11734177
    Abstract: A memory interface for interfacing between a memory bus and a cache memory, comprising: a plurality of bus interfaces configured to transfer data between the memory bus and the cache memory; and a plurality of snoop processors configured to receive snoop requests from the memory bus; wherein each snoop processor is associated with a respective bus interface and each snoop processor is configured, on receiving a snoop request, to determine whether the snoop request relates to the bus interface associated with that snoop processor and to process the snoop request in dependence on that determination.
    Type: Grant
    Filed: August 26, 2021
    Date of Patent: August 22, 2023
    Assignee: Imagination Technologies Limited
    Inventors: Martin John Robinson, Mark Landers
  • Patent number: 11733865
    Abstract: One or more techniques and/or systems are provided for dynamically provisioning logical storage pools of storage devices for applications. For example, a logical storage pool, of one or more storage devices, may be constructed based upon a service level agreement for an application (e.g., an acceptable latency, an expected throughput, etc.). Real-time performance statistics of the logical storage pool may be collected and evaluated against the service level agreement to determine whether a storage device does not satisfy the service level agreement. For example, a latency of a storage device within the logical storage pool may increase overtime as log files and/or other data of the application increase. Accordingly, a new logical storage pool may be automatically and dynamically defined and provisioned for the application to replace the logical storage pool. The new logical storage pool may comprise storage devices expected to satisfy the storage level agreement.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: August 22, 2023
    Assignee: NetApp, Inc.
    Inventors: Sachithananthan Kesavan, Rajesh Nagarajan, Nandakumar Ravindranath Allu
  • Patent number: 11709599
    Abstract: A memory controller connectable to a semiconductor memory including a plurality of memory areas, includes a counter circuit configured to count a degree of wear of each of the memory areas in response to a memory operation addressed thereto, and a control circuit configured to set a rate of for wear leveling to be performed on the plurality of memory areas based on a total number of memory operations performed thereon, and select whether to perform wear leveling on each of the memory areas based on the rate, the degree of wear counted for the memory area, a first threshold for the degree of wear, and a second threshold for the degree of wear. The second threshold is greater than the first threshold.
    Type: Grant
    Filed: August 26, 2021
    Date of Patent: July 25, 2023
    Assignee: Kioxia Corporation
    Inventors: Shohei Onishi, Kenta Yasufuku
  • Patent number: 11704054
    Abstract: A method for performing access management of a memory device with aid of buffer usage reduction control and associated apparatus are provided. The method includes: determining whether any host command among a plurality of host commands from a host device is a trim-related read command, wherein the trim-related read command represents a read command indicating that reading from at least one trimmed location is required; in response to the any host command being the trim-related read command, determining an estimated trim-related read operation count regarding a data buffer according to a trimmed range of the at least one trimmed location and a predetermined unit size of accessing the data buffer; writing predetermined trimmed data having the predetermined unit size into the data buffer; and controlling a transmission interface circuit to read the predetermined trimmed data from the data buffer multiple times, for being returned to the host device.
    Type: Grant
    Filed: January 5, 2022
    Date of Patent: July 18, 2023
    Assignee: Silicon Motion, Inc.
    Inventor: An-Pang Li
  • Patent number: 11698756
    Abstract: Various embodiments described herein provide for selectively sending a cache-based read command, such as a speculative read (SREAD) command in accordance with a Non-Volatile Dual In-Line Memory Module-P (NVDIMM-P) memory protocol, to a memory sub-system.
    Type: Grant
    Filed: February 28, 2022
    Date of Patent: July 11, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Dhawal Bavishi, Patrick A. La Fratta
  • Patent number: 11698854
    Abstract: A data storage device coupled to a controller. The controller is configured to determine whether a request to perform a data transfer operation has been received and determine whether a request to perform a garbage collection operation is necessary during the data transfer operation. The controller generates an extended logical-to-physical table (L2P) including information for the data transfer operation in response to determining the request to perform the data transfer operation has been received and the request to perform the garbage collection operation is necessary, transmits the extended L2P table to one or more peer data storage devices, and performs the garbage collection operation after transmitting the extended L2P table to the one or more peer data storage devices.
    Type: Grant
    Filed: August 25, 2021
    Date of Patent: July 11, 2023
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Senthil Kumar Veluswamy, Lingaraj Bal
  • Patent number: 11693605
    Abstract: A storage device includes a nonvolatile memory device; and a controller configured to, sequentially receive first read commands and a first write command, the first write command being associated with first write data, slice the first write command to generate a plurality of sub-commands, slice the first write data to generate a plurality of sub-data elements, and alternately transmit, to the nonvolatile memory device, at least one read command of the first read commands, and one sub-command of the plurality of sub-commands and one sub-data element of the plurality of sub-data elements.
    Type: Grant
    Filed: May 4, 2021
    Date of Patent: July 4, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jesuk Yeon, Seontaek Kim, Young-Ho Park, Eun Ju Choi, Yonghwa Lee
  • Patent number: 11681554
    Abstract: A workload distribution scheme is provided for a multicore memory system. The memory system includes a memory device including blocks and a controller including cores. The controller receives multiple logical addresses from a host, determines a range of logical addresses among the multiple logical addresses to be allocated for the cores, and distributes multiple subsets of the logical addresses in the range to the cores, based on an operation of modulo and shuffling on the multiple logical addresses.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: June 20, 2023
    Assignee: SK hynix Inc.
    Inventors: Aliaksei Tolstsikau, Maksim Skurydzin
  • Patent number: 11669262
    Abstract: The present disclosure relates to a method, device and product for managing scrubbing operations in a storage system. In the method for managing scrubbing operations in a storage system, regarding a plurality of extents included in the storage system, respective usage states of the plurality of extents are obtained. A group of target extents in which a failure will occur are detected from the plurality of extents based on the respective usage states of the plurality of extents. A scrubbing interval of the scrubbing operations to be performed on the storage system is adjusted according to the detected group of target extents. A scrubbing operation is performed on at least one part of the plurality of extents in the storage system according to the adjusted scrubbing interval, so as to identify a failed extent.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: June 6, 2023
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventor: Bing Liu
  • Patent number: 11669268
    Abstract: An information processing apparatus which implements a rebuild process for restoring a mirroring state even when each of a plurality of connected external storage devices is configured to input and output data to and from a host controller by accessing a storage area of the host controller. When the host controller has issued an instruction to carry out the rebuild process in which data in one of the external storage devices is copied to the other one, one of the external storage devices which is about to write data to the storage area of the host controller for the rebuild process is caused to write the data to the buffer provided in the bridge device, and the other one which is about to read data from the storage area of the host controller for the rebuild process is caused to read the data from the buffer.
    Type: Grant
    Filed: January 7, 2021
    Date of Patent: June 6, 2023
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Daisuke Matsunaga