Patents Examined by Nathan Milakovich
  • Patent number: 11612057
    Abstract: A package includes a conductive pad, with a plurality of openings penetrating through the conductive pad. A dielectric layer encircles the conductive pad. The dielectric layer has portions filling the plurality of openings. An Under-Bump Metallurgy (UBM) includes a via portion extending into the dielectric layer to contact the conductive pad. A solder region is overlying and contacting the UBM. An integrated passive device is bonded to the UBM through the solder region.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: March 21, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Hsien Hsieh, Chi-Hsi Wu, Chen-Hua Yu, Der-Chyang Yeh, Hsien-Wei Chen, Li-Han Hsu, Wei-Cheng Wu
  • Patent number: 11610739
    Abstract: A multilayer ceramic capacitor includes a ceramic body including dielectric layers, a plurality of internal electrodes disposed in the ceramic body, and a first side margin portion and a second side margin portion respectively arranged on end portions of the internal electrodes exposed to first and second surfaces. The first and second side margin portions each include a first region adjacent to an outward facing side surface of the respective side margin portion, and a second region adjacent to the internal electrodes exposed to the first and second surfaces of the ceramic body, and an average size of dielectric grains included in the second region is larger than an average size of dielectric grains included in the first region.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: March 21, 2023
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jong Ho Lee, Yong Park, Ki Pyo Hong, Sim Chung Kang
  • Patent number: 11605502
    Abstract: A multilayer electronic component includes a body including a dielectric layer and a plurality of internal electrodes laminated with the dielectric layer interposed therebetween; and an external electrode disposed on the body and connected to the plurality of internal electrodes. The plurality of internal electrodes includes two or more internal electrodes having different thicknesses, a most thick internal electrode having a greatest thickness and a least thick internal electrode having a lowest thickness among the plurality of internal electrodes are disposed on first and second outermost sides opposing each other in a lamination direction of the plurality of internal electrodes. Each internal electrode disposed between the most thick internal electrode and the least thick internal electrode has a thickness the same as or greater than a thickness of an adjacent internal electrode, which is adjacent to that internal electrode in the lamination direction toward the second outermost side.
    Type: Grant
    Filed: May 25, 2021
    Date of Patent: March 14, 2023
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Hye Sung Pyo, Ho In Jun, Ki Hun Jeon, Do Hyun Hong
  • Patent number: 11600440
    Abstract: A multilayer ceramic capacitor includes: a laminate including dielectric layers and internal electrode layers; and external electrodes on the main surfaces of the laminate. The laminate further includes a first via conductor, a second via conductor, a third via conductor, and a fourth via conductor that connect the internal electrode layers and the external electrodes. The external electrodes include first external electrodes, second external electrodes, third external electrodes, and fourth external electrodes, each connected to the respective end surfaces of the via conductor. Each of the external electrodes does not extend to the side surfaces of the laminate. A ratio W/L of a dimension W in the width direction of the multilayer ceramic capacitor to a dimension L in the length direction of the multilayer ceramic capacitor is about 0.85 or more and about 1 or less. The dimension L in the length direction of the multilayer ceramic capacitor is about 750 ?m or smaller.
    Type: Grant
    Filed: December 11, 2020
    Date of Patent: March 7, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Suguru Nakano, Satoshi Muramatsu, Risa Hojo, Yoshiyuki Nomura
  • Patent number: 11587731
    Abstract: An electronic component includes a laminate in which first internal electrodes and second internal electrodes are alternately laminated in a lamination direction with dielectric layers interposed therebetween, the laminate including a first main surface and a second main surface opposite to each other in the lamination direction, a first side surface and a second side surface opposite to each other in a width direction, and a first end surface and a second end surface opposite to each other in a length direction, a first external electrode provided on a surface of the laminate and electrically connected to the first internal electrodes, a second external electrode provided on a surface of the laminate and electrically connected to the second internal electrodes, and side margin portions each including a dielectric including Ca, Zr, and Ti.
    Type: Grant
    Filed: December 8, 2021
    Date of Patent: February 21, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Eiji Teraoka, Hirokazu Takashima
  • Patent number: 11581140
    Abstract: A ceramic electronic component includes a multilayer chip having a substantially rectangular parallelepiped shape and including dielectric layers and internal electrode layers that are alternately stacked, the internal electrode layers being alternately exposed to two edge faces of the multilayer chip facing each other, and a pair of external electrodes respectively formed on the two edge faces so as to be connected to the internal electrode layers exposed on the respective edge faces, each external electrode extending to at least one side face of the multilayer chip, wherein in the multilayer chip, oxides including Zn and Ni are present around the internal electrode layer in a vicinity of a connection part connecting the internal electrode layer to the external electrode.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: February 14, 2023
    Assignee: TAIYO YUDEN CO., LTD.
    Inventors: Tomoaki Nakamura, Mikio Tahara, Sadanori Shimoda
  • Patent number: 11569039
    Abstract: An electronic component includes a body including a plurality of stacked dielectric layers and internal electrodes disposed with a corresponding dielectric layer interposed therebetween, and external electrodes disposed on the body and connected to corresponding internal electrodes. One of the internal electrodes includes a particle including Ni and Sn and a graphene layer disposed at a boundary of the particle. A ratio of an Sn content to a total content of Ni and Sn is Sn/(Ni+Sn), Sn/(Ni+Sn) of a first region located inside the particle at a first distance from a boundary between the particle and the graphene layer is A1, Sn/(Ni+Sn) of a second region located inside the particle at a second distance from a boundary between the particle and the graphene layer is A2, the second distance is smaller than the first distance, and A1 is smaller than A2.
    Type: Grant
    Filed: July 14, 2021
    Date of Patent: January 31, 2023
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Sang Moon Lee, Jae Young Na, Eun Kwang Lee, Won Hee Yoo
  • Patent number: 11562862
    Abstract: The nonaqueous electrolyte energy storage device according to an aspect of the present invention includes a negative electrode including graphite and graphitizable carbon, in which a ratio of a mass of the graphitizable carbon to a total mass of the graphite and the graphitizable carbon is less than 26% by mass, and a median diameter of the graphitizable carbon is smaller than a median diameter of the graphite.
    Type: Grant
    Filed: April 27, 2021
    Date of Patent: January 24, 2023
    Assignee: GS Yuasa International Ltd.
    Inventor: Suguru Chizawa
  • Patent number: 11564317
    Abstract: In one embodiment, an apparatus generally comprises a printed circuit board comprising a first side, a second side, and a plurality of power vias extending from the first side to the second side, the first side configured for receiving an application specific integrated circuit (ASIC), and a power delivery board mounted on the second side of the printed circuit board and comprising a power plane interconnected with power vias in the power delivery board to electrically couple voltage regulator modules and the ASIC. The voltage regulator modules are mounted on the second side of the printed circuit board.
    Type: Grant
    Filed: April 1, 2021
    Date of Patent: January 24, 2023
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Shobhana Punjabi, Kan Seto, Straty Argyrakis, Joel Richard Goergen, Paul Lachlan Mantiply, Richard Anthony O'Brien
  • Patent number: 11557439
    Abstract: A multi-layer ceramic electronic component includes: a ceramic body including first and second main surfaces facing in a first axis direction, first and second end surfaces facing in a second axis direction, and first and second internal electrodes; a first external electrode including a first cover portion covering the first end surface, and a first extended portion extending from the first cover portion to the second main surface; and a second external electrode including a second cover portion covering the second end surface, and a second extended portion extending from the second cover portion to the second main surface, the multi-layer ceramic electronic component satisfying that, when T1 represents a dimension of the ceramic body in the first axis direction and T2 represents a dimension of each extended portion in the first axis direction, T1+T2 is 50 ?m or less, and T2/(T1+T2) is 0.32 or less.
    Type: Grant
    Filed: April 22, 2021
    Date of Patent: January 17, 2023
    Assignee: Taiyo Yuden Co., Ltd.
    Inventors: Yasutomo Suga, Masataka Watabe, Takeshi Nakajima, Yuji Tomizawa, Toshiya Kuji
  • Patent number: 11551875
    Abstract: A multilayer ceramic electronic component includes: a ceramic body including a dielectric layer and first and second internal electrodes stacked to be alternately exposed to one side surface and the other side surface with the dielectric layer disposed therebetween; and first and second external electrodes disposed on an external surface of the ceramic body to be connected to the first and second internal electrodes, respectively, in which the ceramic body includes an area of overlap in a thickness direction of the first and second internal electrodes, margin region, and/or cover region, and the margin region in the width direction and/or the cover region includes a phosphoric acid-based second phase.
    Type: Grant
    Filed: January 21, 2021
    Date of Patent: January 10, 2023
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Sim Chung Kang, Eun Jung Lee, Ki Pyo Hong, Yong Park
  • Patent number: 11552422
    Abstract: A bulkhead passthrough connector containing a printed circuit board (PCB) for transferring electrical signals across a bulkhead to an electronic valve actuator, an electronic valve actuator configured to operate and communicate with a valve using a PCB through a bulkhead, the electronic valve actuator, and a method of assembling a bulkhead passthrough connector incorporating a PCB. The embodiments may include a passthrough partition which separates one side of the bulkhead from another. A PCB retainer may also be secured to the passthrough partition. The PCB is attached to the PCB retainer and extends from one side to another side of the bulkhead through the passthrough partition. The PCB further includes electrical paths printed on the PCB and electrical connectors located on both sides of the bulkhead to enable communication with external devices.
    Type: Grant
    Filed: June 9, 2021
    Date of Patent: January 10, 2023
    Assignee: FLOWSERVE MANAGEMENT COMPANY
    Inventors: Michael Gorbutt, William Hooss, Dan Morris
  • Patent number: 11552353
    Abstract: A hybrid power supply circuit, a method using a hybrid power supply circuit and method for producing a hybrid power supply circuit are disclosed. In an embodiment a hybrid power-supply circuit includes a first energy-storage device and a second energy-storage device, wherein the first and second energy-storage devices are combined in a module and electrically interconnected, and wherein the first energy-storage device is a solid-state accumulator.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: January 10, 2023
    Assignee: TDK Electronics AG
    Inventors: Stefan Koestner, Masahiro Oishi
  • Patent number: 11545305
    Abstract: An electrolytic capacitor includes a capacitor element, a solid electrolyte layer, an electrolyte solution. The capacitor element has an anode foil with a dielectric layer, and a cathode foil. The solid electrolyte layer is provided between the anode foil and the cathode foil. And the capacitor element is impregnated with the electrolyte solution. The cathode foil includes a covering layer that contains at least one metal selected from titanium and nickel or a compound of the at least one metal. And the solid electrolyte layer contains a conductive polymer, a polymer dopant, and a base component.
    Type: Grant
    Filed: August 25, 2021
    Date of Patent: January 3, 2023
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Tatsuji Aoyama, Kazuhiro Takatani, Kazunari Imamoto, Yoshiaki Ishimaru
  • Patent number: 11538631
    Abstract: A dielectric composition includes a main ingredient having a perovskite structure represented by ABO3, where A is at least one of Ba, Sr, and Ca and B is at least one of Ti, Zr, and Hf, and a first accessory ingredient. The first accessory ingredient comprises 0.1 mole or more of a rare earth element, 0.02 mole or more of Nb, and 0.25 mole or more and 0.9 mole or less of Mg, a sum of contents of the rare earth element and Nb is 1.5 mole or less.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: December 27, 2022
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Tae Young Ham, Ji Hong Jo, Seung In Baik, Hyung Soon Kwon
  • Patent number: 11532434
    Abstract: A ceramic electronic device includes: a multilayer chip having a multilayer structure and a cover layer, the multilayer structure having a structure in which each of dielectric layers and each of internal electrode layers are alternately stacked, respective one ends of the plurality of internal electrode layers being alternately exposed to a first end face and a second end face of the multilayer structure, the cover layer being provided on each of an upper face and a lower face of the multilayer structure in a stacking direction of the multilayer structure, a main component of the cover layer being ceramic, wherein in each of two side faces of the multiplayer structure, a color of a first region is different from a color of a second region that is positioned at a height different from the first region in the stacking direction.
    Type: Grant
    Filed: February 20, 2020
    Date of Patent: December 20, 2022
    Assignee: TAIYO YUDEN CO., LTD.
    Inventor: Atsushi Imai
  • Patent number: 11527358
    Abstract: A multilayer ceramic electronic component includes a ceramic body comprising dielectric layers and first and second internal electrodes laminatedly disposed in a third direction with respective dielectric layers interposed therebetween, and first electrode and second external electrodes disposed on both surfaces of the ceramic body in the first direction and electrically connected to the first and second internal electrodes. When an absolute value of a horizontal angle in the second direction of the first internal electrode with respect to the first surface of the ceramic body is referred to a first angle of the internal electrode, a total sum of the first angles is less than 10°.
    Type: Grant
    Filed: June 16, 2021
    Date of Patent: December 13, 2022
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Hwi Dae Kim, Ji Hong Jo, Woo Chul Shin, Sang Soo Park, Chan Yoon
  • Patent number: 11521799
    Abstract: Each of a supporting-terminal-equipped capacitor chip and a mounted structure thereof includes a capacitor chip and first and second supporting terminals that each have electric conductivity. A maximum diameter size of the first supporting terminal when viewed in an axial direction is larger than a maximum length size of a portion of a first outer electrode on a second main surface in a length direction. A maximum diameter size of the second supporting terminal when viewed in the axial direction is larger than a maximum length size of a portion of a second outer electrode on the second main surface in the length direction.
    Type: Grant
    Filed: October 21, 2020
    Date of Patent: December 6, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Shinobu Chikuma
  • Patent number: 11515090
    Abstract: A ceramic electronic component includes a ceramic body and an external electrode including an end surface region on an end surface of the ceramic body and a side surface region on a side surface of the ceramic body. The side surface region includes a first end portion electrically connected to the end surface region, and a second end portion opposite to the first end portion. At at least a portion where an internal electrode is led out, the end surface region includes a high glass content layer in contact with the ceramic body. At least the second end portion and a vicinity thereof includes a low glass content layer in contact with the ceramic body. At least a portion of the side surface region includes a surface with the low glass content layer exposed.
    Type: Grant
    Filed: April 27, 2021
    Date of Patent: November 29, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Shunsuke Takeuchi
  • Patent number: 11516935
    Abstract: A method for maintaining continuity of a network signal path extending along a backplane includes providing a bypass signal circuit compatible with the network signal path and being electrically connected in series with the first and second portions of the network signal path. The bypass signal circuit includes a normally open circuit portion and an electrical contact movable with respect to the bypass signal circuit. An electrical contact is mechanically moved out of contact with the bypass signal circuit and moved mechanically into contact with the bypass signal circuit in response to the function module being detached from or attached to the function module electrical connector and not in response to an electrical control signal.
    Type: Grant
    Filed: November 3, 2020
    Date of Patent: November 29, 2022
    Assignee: Phoenix Contact Development and Manufacturing, Inc.
    Inventors: Scott Michael Frye, Brian John Gillespie, Christopher Michael Brink