Patents Examined by Neil R Prasad
  • Patent number: 12183686
    Abstract: Disclosed is a method for producing an electronic component, the method including: disposing a plurality of electronic components on an adhesive layer of a composite substrate including a support, a temporary fixing material layer, and the adhesive layer with a connection part in contact with the adhesive layer interposed between the adhesive layer and the electronic components; fixing the plurality of electronic components to the composite substrate by curing the adhesive layer; forming a sealing layer sealing the electronic components; obtaining a sealed structure by peeling off the temporary fixing material layer from the adhesive layer; and a forming a circuit surface by grinding the sealed structure from the adhesive layer side. The plurality of electronic components include an IC chip and a chip-type passive component.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: December 31, 2024
    Assignee: RESONAC CORPORATION
    Inventors: Tomoaki Shibata, Tsuyoshi Ogawa, Xinrong Li
  • Patent number: 12170304
    Abstract: An imaging element has at least a photoelectric conversion section, a first transistor TR1, and a second transistor TR2, the photoelectric conversion section includes a photoelectric conversion layer 13, a first electrode 11, and a second electrode 12, the imaging element further has a first photoelectric conversion layer extension section 13A, a third electrode 51, and a fourth electrode 51C, the first transistor TR1 includes the second electrode 12 that functions as one source/drain section, the third electrode that functions as a gate section 51, and the first photoelectric conversion layer extension section 13A that functions as the other source/drain section, and the first transistor TR1 (TRrst) is provided adjacent to the photoelectric conversion section.
    Type: Grant
    Filed: May 15, 2023
    Date of Patent: December 17, 2024
    Assignee: Sony Semiconductor Solutions Corporation
    Inventor: Fumihiko Koga
  • Patent number: 12170251
    Abstract: Disclosed is a semiconductor package comprising a redistribution substrate that has a first trench that extends through a top surface of the redistribution substrate, a first semiconductor chip on the redistribution substrate, a capacitor chip on a bottom surface of the first semiconductor chip, and an under-fill layer on the bottom surface of the first semiconductor chip. The redistribution substrate includes a plurality of dielectric layers vertically stacked, a plurality of redistribution patterns in each of the dielectric layers, and a plurality of dummy redistribution patterns in the first trench. The dummy redistribution patterns vertically overlap the first semiconductor chip. An uppermost surface of the dummy redistribution pattern is located at a level higher than a level of a bottom surface of the first trench.
    Type: Grant
    Filed: May 11, 2021
    Date of Patent: December 17, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyoung Lim Suk, Seokhyun Lee, Jaegwon Jang
  • Patent number: 12170261
    Abstract: An electronic assembly may include a component comprising conductive studs disposed over an active layer of the component. A first encapsulant layer may be disposed around four side surfaces of the component, over the active layer of the component, and contacting at least a portion of the sides of the conductive studs. A substantially planar surface may be disposed over the active layer of the component, wherein the substantially planar surface comprises ends of the conductive studs and the first encapsulant layer. The first encapsulant layer comprises a roughness less than 500 nanometers. First conductive elements may be disposed over the encapsulant and coupled with the conductive studs. A second layer of encapsulant may be disposed over the first conductive elements.
    Type: Grant
    Filed: May 9, 2023
    Date of Patent: December 17, 2024
    Assignee: Deca Technologies USA, Inc.
    Inventors: Robin Davis, Timothy L Olson, Craig Bishop, Clifford Sandstrom, Paul R. Hoffman
  • Patent number: 12165989
    Abstract: A semiconductor package includes a multilayer package substrate including a first layer including a first dielectric and first metal layer including a first metal trace and a second layer including a second dielectric layer. An integrated circuit (IC) die includes bond pads, with a bottom side of the IC die attached to the first metal trace. Metal pillars are through the second dielectric layer connecting to the first metal trace. A third layer on the second layer includes a third dielectric layer on the second layer extending to a bottom side of the semiconductor package, and a second metal layer including second metal traces including inner second metal traces connected to the bond pads and outer second metal traces over the metal pillars, and filled vias providing externally accessible contact pads that connect the second metal traces to a bottom side of the semiconductor package.
    Type: Grant
    Filed: April 3, 2023
    Date of Patent: December 10, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jie Chen, Yiqi Tang, Rajen Murugan, Liang Wan
  • Patent number: 12165988
    Abstract: An electronic device includes a substrate comprising outward terminals. An electronic component is connected to the outward terminals. External interconnects are connected to the outward terminals and include a first external interconnect connected to a first outward terminal. A lower shield is adjacent to the substrate bottom side and is laterally between the external interconnects. The lower shield is electrically isolated from the first external interconnect by one or more of 1) a dielectric buffer interposed between the lower shield and the first external interconnect; or 2) the lower shield including a first part and a second part, the first part being laterally separated from the second part by a first gap, wherein the first part laterally surrounds lateral sides of the first external interconnect; and the second part is vertically interposed between the first outward terminal and the first external interconnect.
    Type: Grant
    Filed: June 16, 2023
    Date of Patent: December 10, 2024
    Assignee: Amkor Technology Singapore Holding Pte. Ltd.
    Inventors: Min Won Park, Tae Yong Lee, Ji Hun Yi, Cheol Ho Lee
  • Patent number: 12165961
    Abstract: A semiconductor package structure having a frontside redistribution layer, a stacking structure disposed over the frontside redistribution layer and having a first semiconductor die and a second semiconductor die over the first semiconductor die. A backside redistribution layer is disposed over the stacking structure, a first intellectual property (IP) core is disposed in the stacking structure and electrically coupled to the frontside redistribution layer through a first routing channel. A second IP core is disposed in the stacking structure and is electrically coupled to the backside redistribution layer through a second routing channel, wherein the second routing channel is different from the first routing channel and electrically insulated from the frontside redistribution layer.
    Type: Grant
    Filed: June 6, 2023
    Date of Patent: December 10, 2024
    Assignee: MEDIATEK INC.
    Inventors: Hsing-Chih Liu, Zheng Zeng, Che-Hung Kuo
  • Patent number: 12125832
    Abstract: In one example, a semiconductor device comprises a base assembly comprising a first substrate, a first device on a top surface of the first substrate, and a first encapsulant on the top surface of the first substrate and bounding a side surface of the first device. The semiconductor device further comprises a conductive pillar on the first substrate and in the first molding compound, wherein the conductive pillar comprises a non-conductive pillar core and a conductive pillar shell on the pillar core.
    Type: Grant
    Filed: October 26, 2021
    Date of Patent: October 22, 2024
    Assignee: Amkor Technology Singapore Holding Pte. Ltd.
    Inventors: In Su Mok, Won Geol Lee, Il Bok Lee, Won Myoung Ki
  • Patent number: 12125794
    Abstract: A semiconductor device includes a semiconductor substrate, a dielectric structure, an electrical insulating and thermal conductive layer, an etch stop layer and a circuit layer. The electrical insulating and thermal conductive layer is disposed over the semiconductor substrate. The etch stop layer includes silicon nitride and is disposed between the semiconductor substrate and the electrical insulating and thermal conductive layer. The dielectric structure is disposed over the electrical insulating and thermal conductive layer, wherein a thermal conductivity of the electrical insulating and thermal conductive layer is substantially greater than a thermal conductivity of the dielectric structure. The circuit layer is disposed in the dielectric structure.
    Type: Grant
    Filed: February 12, 2023
    Date of Patent: October 22, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hang Tung, Chen-Hua Yu, Tung-Liang Shao, Su-Chun Yang, Wen-Lin Shih
  • Patent number: 12119305
    Abstract: A semiconductor package includes a redistribution substrate including a first redistribution layer; a semiconductor chip electrically connected to the first redistribution layer; a vertical connection structure adjacent a periphery of the semiconductor chip and electrically connected to the first redistribution layer; and an encapsulant on the vertical connection structure. The vertical connection structure includes a metal pillar having a bottom surface facing the redistribution substrate, a top surface positioned opposite to the bottom surface, and a side surface positioned between the bottom surface and the top surface. The vertical connection structure further includes a plating layer on each of the bottom surface, the top surface, and the side surface of the metal pillar, and having a roughened surface.
    Type: Grant
    Filed: January 29, 2023
    Date of Patent: October 15, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyungdon Mun, Myungsam Kang, Youngchan Ko, Yieok Kwon, Jeongseok Kim, Gongje Lee, Bongju Cho
  • Patent number: 12119352
    Abstract: An integrated circuit (IC) structure, a switch and related method, are disclosed. The IC structure includes an active device, e.g., a switch, over a bulk semiconductor substrate, and an isolation structure under the active device in the bulk semiconductor substrate. The isolation structure may include a trench isolation adjacent the active device in the bulk semiconductor substrate, a dielectric layer laterally adjacent the trench isolation and over the active device, and a porous semiconductor layer in the bulk semiconductor substrate under the dielectric layer laterally adjacent the trench isolation. The IC structure employs a lower cost, low resistivity bulk semiconductor substrate rather than a semiconductor-on-insulator (SOI) substrate, yet it has better performance characteristics for RF switches than an SOI substrate.
    Type: Grant
    Filed: January 6, 2022
    Date of Patent: October 15, 2024
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Uzma B. Rana, Steven M. Shank, Anthony K. Stamper
  • Patent number: 12119309
    Abstract: When III-V semiconductor material is bonded to an oxide material, water molecules can degrade the bonding if they become trapped at the interface between the III-V material and the oxide material. Because water molecules can diffuse readily through oxide material, and may not diffuse as readily through III-V material or through silicon, forcing the III-V material against the oxide material can force water molecules at the interface into the oxide material and away from the interface. Water molecules present at the interface can be forced during manufacturing through vertical channels in a silicon layer into a buried oxide layer thereby to enhance bonding between the III-V material and the oxide material. Water molecules can be also forced through lateral channels in the oxide material, past a periphery of the III-V material, and, through diffusion, out of the oxide material into the atmosphere.
    Type: Grant
    Filed: March 1, 2022
    Date of Patent: October 15, 2024
    Assignee: OpenLight Photonics, Inc.
    Inventors: Avi Feshali, John Hutchinson
  • Patent number: 12114552
    Abstract: Device structures are provided that include one or more plasmonic OLEDs and zero or more non-plasmonic OLEDs. Each plasmonic OLED includes an enhancement layer that includes a plasmonic material which exhibits surface plasmon resonance that non-radiatively couples to an organic emissive material and transfers excited state energy from the emissive material to a non-radiative mode of surface plasmon polaritons in the plasmonic OLED.
    Type: Grant
    Filed: April 6, 2023
    Date of Patent: October 8, 2024
    Assignee: Universal Display Corporation
    Inventors: Nicholas J. Thompson, Michael Stuart Weaver, Michael Fusella
  • Patent number: 12113070
    Abstract: Structures including a vertical heterojunction bipolar transistor and methods of forming a structure including a vertical heterojunction bipolar transistor. The structure comprises a semiconductor substrate including a trench, a first semiconductor layer including a portion adjacent to the trench, a dielectric layer between the first semiconductor layer and the semiconductor substrate, and a second semiconductor layer in the trench. The dielectric layer has an interface with the first semiconductor layer, and the second semiconductor layer includes a portion that is recessed relative to the interface. The structure further comprises a vertical heterojunction bipolar transistor including a collector in the portion of the second semiconductor layer.
    Type: Grant
    Filed: June 2, 2022
    Date of Patent: October 8, 2024
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Peter Baars, Viorel Ontalus, Ketankumar H. Tailor, Michael Zier, Crystal R. Kenney, Judson Holt
  • Patent number: 12102013
    Abstract: A magnetic detection device includes a first magnetic sensor, a second magnetic sensor, and a resin body. The first magnetic sensor includes a first sealing body and first terminals. The second magnetic sensor includes a second sealing body and second terminals. The resin body includes a resin-body main body, first wiring lines, and second wiring lines. Each of the first wiring lines includes a first overlapping portion overlapping with corresponding one of the first terminals. As viewed in a normal direction of each of the first terminals, the first overlapping portion is arranged at a position shifted from all of the second terminals and the second wiring lines. Each of the first wiring lines is welded to corresponding one of the first terminals at the first overlapping portion.
    Type: Grant
    Filed: December 22, 2021
    Date of Patent: September 24, 2024
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yusuke Kato, Tetsuo Amano, Hideki Shimauchi, Akira Koshimizu
  • Patent number: 12094848
    Abstract: Embodiments of the present disclosure provide an integrated circuit die having edge interconnect features. The edge interconnect features may be conductive lines extending through sealing rings and exposed on edge surfaces of the integrated circuit die. The edge interconnect features are configured to connect with other integrated circuit dies without going through an interposer. The semiconductor device may include two or more integrated circuit dies with edge interconnect features and connected through a RDL structure formed between the two or more integrated circuit dies.
    Type: Grant
    Filed: July 22, 2021
    Date of Patent: September 17, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shin-Yi Yang, Ming-Han Lee, Shau-Lin Shue
  • Patent number: 12087833
    Abstract: A semiconductor device includes an active pattern on a substrate, the active pattern extending in a first direction, a gate electrode on the active pattern, the gate electrode extending in a second direction intersecting the first direction and including a first portion and a second portion arranged along the second direction, a first contact plug on the gate electrode, the first contact plug being connected to a top surface of the second portion of the gate electrode, a source/drain region in the active pattern on a sidewall of the gate electrode, and a source/drain contact on the source/drain region, a height of a top surface of the source/drain contact being higher than a top surface of the first portion of the gate electrode and lower than the top surface of the second portion of the gate electrode.
    Type: Grant
    Filed: October 17, 2023
    Date of Patent: September 10, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Heon Bok Lee, Dae Yong Kim, Wan Don Kim, Jeong Hyuk Yim, Won Keun Chung, Hyo Seok Choi, Sang Jin Hyun
  • Patent number: 12080669
    Abstract: A semiconductor device module includes a package carrier having an opening, wherein in the opening there is disposed a semiconductor package including a semiconductor die, an encapsulant, and first vertical contacts, wherein the encapsulant at least partially covers the semiconductor die, and the first vertical contacts are connected to the semiconductor die and extend at least partially through the encapsulant, and a first outer metallic contact layer electrically connected to the first vertical contacts.
    Type: Grant
    Filed: September 23, 2021
    Date of Patent: September 3, 2024
    Assignee: Infineon Technologies Austria AG
    Inventors: Edward Fuergut, Martin Gruber, Petteri Palm, Bernd Schmoelzer, Wolfgang Scholz, Mark Thomas
  • Patent number: 12074148
    Abstract: A semiconductor package includes a first package component comprising: a first semiconductor die; a first encapsulant around the first semiconductor die; and a first redistribution structure electrically connected to the semiconductor die. The semiconductor package further includes a second package component bonded to the first package component, wherein the second package component comprises a second semiconductor die; a heat spreader between the first semiconductor die and the second package component; and a second encapsulant between the first package component and the second package component, wherein the second encapsulant has a lower thermal conductivity than the heat spreader.
    Type: Grant
    Filed: December 2, 2022
    Date of Patent: August 27, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Fong-Yuan Chang, Po-Hsiang Huang, Lee-Chung Lu, Jyh Chwen Frank Lee, Yii-Chian Lu, Yu-Hao Chen, Keh-Jeng Chang
  • Patent number: 12068273
    Abstract: A package includes a die and a redistribution layer. A top surface of the die has a first area and a second area connected with the first area. The redistribution layer structure includes a first insulation layer, a redistribution layer, and a second insulation layer. The first insulation layer is overlapping with the second area. The redistribution layer is disposed above the die. The second insulation layer is disposed above the redistribution layer and overlapping with the second area and the first area. The second insulation layer covers a top surface of the first insulation layer and is in contact with a side surface of the first insulation layer and the top surface of the die.
    Type: Grant
    Filed: February 10, 2023
    Date of Patent: August 20, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tian Hu, Hung-Jui Kuo, Yu-Hsiang Hu, Sih-Hao Liao