Patents Examined by Neil R Prasad
  • Patent number: 11417613
    Abstract: A semiconductor package includes: a frame substrate having a plurality of wiring layers and a cavity; an adhesive member disposed at the bottom of the cavity; a semiconductor chip disposed in the cavity, with a connection pad on an upper surface and the lower surface in contact with the adhesive member; a first conductive bump disposed on the connection pad; a second conductive bump disposed on the uppermost of the plurality of wiring layers; an insulating post disposed in the cavity and whose lower surface contacts the adhesive member; an encapsulant filling the cavity and covering side surfaces of the first and second conductive bumps and the insulating post’ and a redistribution structure disposed on the encapsulant, including a redistribution layer electrically connected to the first and second conductive bumps, wherein the insulating post includes a material having a greater hardness than that of the first and second conductive bumps.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: August 16, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jingu Kim, Shanghoon Seo, Sangkyu Lee, Jeongho Lee
  • Patent number: 11411038
    Abstract: To achieve a size reduction of a semiconductor package while securing stability in mounting. Three terminals t1, t2, and t4 are individually arranged on a semiconductor package 10 having a rectangular shape as viewed in plan in such a manner that the center in the longitudinal direction of the semiconductor package 10 of each of the three terminals t1, t2, and t4 and the center in the longitudinal direction of each of the other terminals are not overlapped with each other as viewed from the side of the long side.
    Type: Grant
    Filed: August 25, 2020
    Date of Patent: August 9, 2022
    Assignee: Asahi Kasei Microdevices Corporation
    Inventors: Osamu Shirata, Yusuke Hidaka
  • Patent number: 11404347
    Abstract: A semiconductor package according to an exemplary embodiment of the present disclosure may comprise a semiconductor chip comprising a chip pad; a redistribution layer electrically connected to the chip pad of the semiconductor chip; an external connection terminal electrically connected to the redistribution layer; a sealing material covering the semiconductor chip and configured to fix the semiconductor chip and the redistribution layer; an adhesive film positioned on the upper surface of the sealing material; and a heat sink formed on the upper surface of the adhesive film and having a stepped portion at the periphery thereof.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: August 2, 2022
    Assignee: NEPES CO., LTD.
    Inventors: Nam Chul Kim, Jong Heon Kim, Eung Ju Lee, Yong Woon Yeo, Chang Woo Lee
  • Patent number: 11398432
    Abstract: A wiring substrate includes a resin layer formed of an insulating resin, a first component, at least a part of which is embedded in the resin layer, a first wiring embedded in the resin layer, the first wiring including an exposed surface exposed from the resin layer at a first surface-side of the resin layer, and a first electrode including a wiring portion and an electrode portion, the wiring portion embedded in the resin layer and connecting to the first component in the resin layer, the electrode portion protruding from the first surface-side of the resin layer to a position higher than the exposed surface of the first wiring.
    Type: Grant
    Filed: May 7, 2020
    Date of Patent: July 26, 2022
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Tetsuichiro Kasahara, Tsukasa Nakanishi
  • Patent number: 11393752
    Abstract: An electronic component includes a first insulating layer, a resistance layer including a metal thin film that is formed on the first insulating layer, the resistance layer having a first end portion, a second end portion and a central portion between the first end portion and the second end portion, a first electrode having a first contact portion and a second contact portion spaced away from the first contact portion both of which are in contact with the resistance layer at a portion of the first end portion side with respect to the central portion of the resistance layer, a notched portion formed in the first end portion of the resistance layer and between the first contact portion and the second contact portion, and a second electrode having a contact portion in contact with the resistance layer at a portion of the second end portion side with respect to the central portion of the resistance layer.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: July 19, 2022
    Assignee: ROHM CO., LTD.
    Inventor: Bungo Tanaka
  • Patent number: 11393750
    Abstract: A semiconductor device includes a substrate, a semiconductor fin, source region, a gate electrode, a source contact, and a source via. The semiconductor fin has a length extending above the substrate. The source region is on the semiconductor fin. The gate electrode has a length across the semiconductor fin. The source contact is above the source region. The source via lands on the source contact and has a first dimension along a lengthwise direction of the semiconductor fin and has a second dimension along a lengthwise direction of the gate electrode from a top view. A ratio of the second dimension to the first dimension of the source via is greater than about 2.
    Type: Grant
    Filed: July 28, 2020
    Date of Patent: July 19, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Jhon-Jhy Liaw
  • Patent number: 11387222
    Abstract: In an embodiment, a structure includes: a processor device including logic devices; a first memory device directly face-to-face bonded to the processor device by metal-to-metal bonds and by dielectric-to-dielectric bonds; a first dielectric layer laterally surrounding the first memory device; a redistribution structure over the first dielectric layer and the first memory device, the redistribution structure including metallization patterns; and first conductive vias extending through the first dielectric layer, the first conductive vias connecting the metallization patterns of the redistribution structure to the processor device.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: July 12, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Hua Yu, Wei Ling Chang, Chuei-Tang Wang, Chieh-Yen Chen
  • Patent number: 11387282
    Abstract: A foldable display apparatus includes: a non-folding area, and a folding area, in which an aperture ratio of a plurality of red sub pixels in the folding area is lower than an aperture ratio of a plurality in red sub pixels of the non-folding area, an aperture ratio of the plurality of green sub pixels in the folding area is lower than an aperture ratio of the plurality of green sub pixels of the non-folding area, and an aperture ratio of the plurality in blue sub pixels of the folding area is lower than an aperture ratio of the plurality of blue sub pixels of the non-folding area.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: July 12, 2022
    Assignee: LG Display Co., Ltd.
    Inventors: Suk Choi, Sinchul Kang, Miyeon Seo
  • Patent number: 11387158
    Abstract: The semiconductor device includes a substrate, a semiconductor element bonded to the substrate, and a sealing resin sealing at least a part of the substrate and the semiconductor element, in which the semiconductor element includes an active region through which a main current flows in an ON state of the semiconductor element, a terminal region surrounding the active region, an anchor film provided on an insulating film of the terminal region, and a protective film covering at least the terminal region including the anchor film, and the anchor film consists of a material different from the insulating film and has a plurality of openings provided discretely.
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: July 12, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventor: Yosuke Nakata
  • Patent number: 11362031
    Abstract: An integrated circuit device includes a conductive line including a metal layer and an insulation capping structure covering the conductive line. The first insulation capping structure includes a first insulation capping pattern that is adjacent to the metal layer in the insulation capping structure and has a first density, and a second insulation capping pattern spaced apart from the metal layer with the first insulation capping pattern therebetween and having a second density that is greater than the first density. In order to manufacture the integrated circuit device, the conductive line having a metal layer is formed on a substrate, a first insulation capping layer having the first density is formed directly on the metal layer, and a second insulation capping layer having the second density that is greater than the first density is formed on the first insulation capping layer.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: June 14, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Choonghyun Lee, Joonyong Choe, Youngju Lee
  • Patent number: 11355404
    Abstract: Mitigating surface damage of probe pads in preparation for direct bonding of a substrate is provided. Methods and layer structures prepare a semiconductor substrate for direct bonding processes by restoring a flat direct-bonding surface after disruption of probe pad surfaces during test probing. An example method fills a sequence of metals and oxides over the disrupted probe pad surfaces and builds out a dielectric surface and interconnects for hybrid bonding. The interconnects may be connected to the probe pads, and/or to other electrical contacts of the substrate. A layer structure is described for increasing the yield and reliability of the resulting direct bonding process. Another example process builds the probe pads on a next-to-last metallization layer and then applies a direct bonding dielectric layer and damascene process without increasing the count of mask layers.
    Type: Grant
    Filed: April 10, 2020
    Date of Patent: June 7, 2022
    Assignee: INVENSAS BONDING TECHNOLOGIES, INC.
    Inventors: Guilian Gao, Laura Wills Mirkarimi, Gaius Gillman Fountain, Jr.
  • Patent number: 11355557
    Abstract: A foldable display apparatus includes: a non-folding area, and a folding area, in which an aperture ratio of a plurality of red sub pixels in the folding area is lower than an aperture ratio of a plurality in red sub pixels of the non-folding area, an aperture ratio of the plurality of green sub pixels in the folding area is lower than an aperture ratio of the plurality of green sub pixels of the non-folding area, and an aperture ratio of the plurality in blue sub pixels of the folding area is lower than an aperture ratio of the plurality of blue sub pixels of the non-folding area.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: June 7, 2022
    Assignee: LG Display Co., Ltd.
    Inventors: Suk Choi, Sinchul Kang, Miyeon Seo
  • Patent number: 11348847
    Abstract: The invention provides a testkey detection circuit, including a plurality of oscillators and a driving circuit. Each of the oscillators has an enable terminal, a voltage terminal and an output terminal, wherein the enable terminals are connected to a common enable terminal. The driving circuit receives the output terminals of the oscillators and increases a driving level of a selected one of the output terminals as a frequency output.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: May 31, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kun-Yuan Wu, Wei-Jen Wang, Chien-Fu Chen, Chen-Hsien Hsu, Yuan-Hui Chen, Ruei-Yau Chen, Cheng-Tsung Ku, Zhi-Hong Huang, Cheng-Yang Tsai, Yu-Lin Chen
  • Patent number: 11342273
    Abstract: Disclosed are a package structure of an integrated passive device and a manufacturing method thereof and a substrate. The method includes: providing an organic frame having a chip embedding cavity and a metal pillar, laminating at least one layer of first dielectric on an upper surface of the organic frame, and processing the first dielectric by photolithography to form an opening correspondingly above the chip embedding cavity; mounting an electronic component in the chip embedding cavity through the opening, the electronic component including an upper and lower electrodes; laminating and curing a second dielectric into the chip embedding cavity and on an upper surface of the first dielectric, thinning the first and second dielectrics to expose the upper and lower electrodes, upper and lower surfaces of the metal pillar; performing metal electroplating to form a circuit layer communicated with the upper and lower electrodes and the metal pillar.
    Type: Grant
    Filed: September 23, 2020
    Date of Patent: May 24, 2022
    Assignee: ZHUHAI ACCESS SEMICONDUCTOR CO., LTD
    Inventors: Xianming Chen, Yejie Hong, Benxia Huang, Lei Feng, Bingsen Xie
  • Patent number: 11329032
    Abstract: A semiconductor device includes a first package, and a second package stacked on the first package. Each of the first and second packages includes a first redistribution substrate having a first redistribution pattern, a first semiconductor chip on the first redistribution substrate and connected to the first redistribution pattern, a first molding layer covering the first semiconductor chip on the first redistribution substrate, a first through-electrode penetrating the first molding layer so as to be connected to the first redistribution pattern, and a second through-electrode penetrating the first molding layer and not connected to the first redistribution pattern. The first redistribution pattern of the second package is electrically connected to the second through-electrode of the first package.
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: May 10, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ae-Nee Jang, Inhyo Hwang
  • Patent number: 11329187
    Abstract: A method of aligning micro LEDs and a method of manufacturing a micro LED display using the same are provided. The method of aligning micro LEDs includes providing micro LEDs, each having a first surface that has a first maximum width and a second surface opposite to the first surface and has a second maximum width that is greater than the first maximum width, providing a transfer substrate including a transfer mold that has an array of openings, each of the openings being configured to accommodate the first surface of a corresponding micro LED and not accommodate the second surface of the corresponding micro LED and aligning the micro LEDs in one direction in the openings of the transfer mold by inserting the micro LEDs into the openings of the transfer mold so that the first surface of each of the micro LEDs is positioned within a corresponding opening.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: May 10, 2022
    Assignees: SAMSUNG ELECTRONICS CO., LTD., SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION
    Inventors: Kyungwook Hwang, Jungel Ryu, Sungjin Kang, Jongmyeong Kim, Jehong Oh, Euijoon Yoon, Seungmin Lee, Junsik Hwang
  • Patent number: 11322502
    Abstract: An apparatus comprising a memory array comprising access lines. Each of the access lines comprises an insulating material adjacent a bottom surface and sidewalls of a base material, a first conductive material adjacent the insulating material, a second conductive material adjacent the first conductive material, and a barrier material between the first conductive material and the second conductive material. The barrier material is configured to suppress migration of reactive species from the second conductive material. Methods of forming the apparatus and electronic systems are also disclosed.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: May 3, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Dojun Kim, Christopher W. Petz, Sanket S. Kelkar, Hidekazu Nobuto
  • Patent number: 11315869
    Abstract: The present application discloses a semiconductor device with a decoupling unit and a method for fabricating the semiconductor device. The semiconductor device includes a substrate including an array area and a peripheral area adjacent to the array area, a first decoupling unit positioned in the peripheral area of the substrate, a storage unit positioned in the array area of the substrate, a redistribution structure positioned above the peripheral area and the array area of the substrate, a middle insulating layer positioned on the redistribution structure positioned above the peripheral area, and a top conductive layer positioned on the middle insulating layer. The redistribution structure positioned above the peripheral area, the middle insulating layer, and the top conductive layer together configure a second decoupling unit.
    Type: Grant
    Filed: December 1, 2020
    Date of Patent: April 26, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Tse-Yao Huang, Shing-Yih Shih
  • Patent number: 11309379
    Abstract: An organic light emitting diode display includes a lower substrate, a sub-pixel structure, an upper substrate, a sealant, and a first power supply wire. The lower substrate has a display area, a peripheral area, and a pad area. The sub-pixel structure is disposed in the display area on the lower substrate. The upper substrate is disposed on the sub-pixel structure. The sealant is disposed in the peripheral area between the lower substrate and the upper substrate. The first power supply wire is disposed between the lower substrate and the sealant, and overlaps the lower substrate and the sealant. The first power supply wire includes a first protrusion protruding in a first direction that is a direction from the pad area to the display area in the first peripheral area.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: April 19, 2022
    Assignee: SAMSUNG DISPLAY CO., LTD
    Inventors: Bongwon Lee, Yanghee Kim, Hyun-Chol Bang, Sujin Lee
  • Patent number: 11309253
    Abstract: A package structure and a method for manufacturing a package structure are provided. The package structure includes a first conductive structure and a second conductive structure. The first conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The second conductive structure is bonded to the first conductive structure. The second conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. A distribution density of the circuit layer of the first conductive structure is greater than a distribution density of the circuit layer of the second conductive structure. A size of the second conductive structure is less than a size of the first conductive structure.
    Type: Grant
    Filed: April 24, 2020
    Date of Patent: April 19, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Chin-Li Kao