Patents Examined by Neil R Prasad
  • Patent number: 10879371
    Abstract: Embodiments described in this disclosure relate to formation of a gate structure of a device, such as in a replacement gate process, and the device formed thereby. In some examples, after an interfacial layer and a gate dielectric layer are deposited, a rapid anneal process, such as laser anneal or flash lamp anneal process, is performed in a controlled ambient nitrogen-containing environment to form a nitrided portion in the gate dielectric layer. The nitrided portion passivates the defects at the surface of the gate dielectric layer and can serve as a barrier to prevent etchant chemistry and defects/dopants from the subsequent gate stack layers from affecting or diffusing through the gate dielectric layer. Particularly, the rapid anneal process is performed on a millisecond scale to confine nitrogen atoms in the gate dielectric layer without diffusing into the underlying interfacial dielectric and/or any neighboring structure such as fin.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: December 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Yun Li, Huicheng Chang, Che-Hao Chang, Hung-Yao Chen, Cheng-Po Chau, Xiong-Fei Yu, Terry Huang
  • Patent number: 10879302
    Abstract: An image sensor may include a photoelectric device configured to selectively absorb light associated with a first color of three primary colors, a semiconductor substrate that is stacked with the photoelectric device and includes first and second photo-sensing devices configured to sense light associated with second and third colors of three primary colors. The first and second photo-sensing devices may have different thicknesses, different depths from a surface of the semiconductor substrate, or different thicknesses and different depths from the surface of the semiconductor substrate. At least one part of a thickness area of the first photo-sensing device may overlap at least one part of a thickness area of the second photo-sensing device in a parallel direction extending substantially parallel to the surface of the semiconductor substrate.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: December 29, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kwang Hee Lee, Gae Hwang Lee, Sung Young Yun, Dong-Seok Leem, Yong Wan Jin
  • Patent number: 10872866
    Abstract: A semiconductor package including a substrate having a surface, and a conductive element on the first surface and electrically coupled to the substrate. The conductive element has a principal axis forming an angle less than 90 degrees with the surface.
    Type: Grant
    Filed: October 8, 2018
    Date of Patent: December 22, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Jenchun Chen
  • Patent number: 10868152
    Abstract: A semiconductor device including a memory cell, the semiconductor device including: a floating gate provided at a semiconductor substrate with a first insulation film inbetween, and including a pointed portion having a pointed end at one end side; a spacer provided at the floating gate; a second insulation film provided between the floating gate and the spacer and that covers a side surface of the spacer at the one end side; and a control gate that contacts a side surface of the floating gate at the one end side via a third insulation film and that contacts the side surface of the spacer at the one end side via the second insulation film and the third insulation film.
    Type: Grant
    Filed: October 8, 2018
    Date of Patent: December 15, 2020
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Akira Chiba
  • Patent number: 10861990
    Abstract: A method of manufacturing an epitaxial silicon wafer that includes growing a silicon single crystal ingot doped with a boron concentration of 2.7×1017 atoms/cm3 or more and 1.3×1019 atoms/cm3 or less by the CZ method; producing a silicon substrate by processing the silicon single crystal ingot; and forming an epitaxial layer on a surface of the silicon substrate. During growing of the silicon single crystal ingot, the pull-up conditions of the silicon single crystal ingot are controlled so that the boron concentration Y (atoms/cm3) and an initial oxygen concentration X (×1017 atoms/cm3) satisfy the expression X??4.3×10?19Y+16.3.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: December 8, 2020
    Assignee: SUMCO CORPORATION
    Inventors: Kazuhisa Torigoe, Toshiaki Ono
  • Patent number: 10862008
    Abstract: A ceramic conversion element, a light-emitting device and a method for producing a ceramic conversion element are disclosed. In an embodiment a ceramic conversion element includes a central region with a structured top surface including a plurality of structure elements and a frame surrounding the central region, the frame having a planar top surface, wherein the central region and the frame are formed as one piece, and wherein the ceramic conversion element is configured to convert primary radiation into secondary radiation of a different wavelength range.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: December 8, 2020
    Assignee: OSRAM OPTO SEMICONDUCTORS GMBH
    Inventors: Darshan Kundaliya, Norwin von Malm, Jeffery J. Serre
  • Patent number: 10854609
    Abstract: Wells formed in a semiconductor device can be discharged faster in a transition from a stand-by state to an active state. The semiconductor device includes an n-type well applied, in an active state, with a power supply voltage and, in a stand-by state, with a voltage higher than the power supply voltage, a p-type well applied, in the active state, with a ground voltage and, in the stand-by state, with a voltage lower than the ground voltage, and a path which, in a transition from the stand-by state to the active state, electrically couples the n-type well and the p-type well.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: December 1, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Akira Tanabe
  • Patent number: 10854278
    Abstract: A structure includes an SRAM cell includes a first and a second pull-up MOS device, and a first and a second pull-down MOS device forming cross-latched inverters with the first pull-up MOS device and the second pull-up MOS device. A first metal layer is over the gate electrodes of the MOS devices in the SRAM cell. The structure further includes a first metal layer, and a CVss landing pad, wherein the CVss landing pad has a portion in the SRAM cell. The CVss landing pas is in a second metal layer over the first metal layer. A word-line is in the second metal layer. A CVss line is in a third metal layer over the second metal layer. The CVss line is electrically coupled to the CVss landing pad.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: December 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jhon Jhy Liaw
  • Patent number: 10840347
    Abstract: Provided is a semiconductor device with negative differential transconductance. The semiconductor device includes a substrate, a gate electrode formed on the substrate, an insulating layer formed on the gate electrode, a source electrode material layer formed on the insulating layer, a semiconductor material layer formed on the insulating layer to be hetero-joined to the source electrode material layer, a source electrode formed on the source electrode material layer, and a drain electrode formed on the semiconductor material layer. A work function of the source electrode material layer is controlled by a gate voltage applied through the gate electrode, and the source electrode material layer shows negative differential transconductance depending on a level of the gate voltage.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: November 17, 2020
    Assignee: Research & Business Foundation Sungkyunkwan University
    Inventors: Jin Hong Park, Jaewoo Shim, Dong Ho Kang
  • Patent number: 10825800
    Abstract: A semiconductor package including a package base substrate; at least one semiconductor chip on the package base substrate; a heat sink attached on the at least one semiconductor chip, the heat sink including a base and a plurality of protrusion patterns on a top of the base; and a molding covering a top of the package base substrate, a side surface of the at least one semiconductor chip, and a side surface of the heat sink without covering a top of the heat sink.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: November 3, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Tae-sung Kim, Cheol-woo Lee
  • Patent number: 10825861
    Abstract: An embodiment includes an apparatus comprising: first and second electrodes; first and second insulation layers between the first and second electrodes; and a middle layer between the first and second insulation layers; wherein (a) the middle layer includes material that has a first resistance when the first electrode is biased at a first voltage level and a second resistance when the first electrode is biased at a second voltage level; (b) the first resistance is less than the second resistance and the first voltage level is greater than the second voltage level. Other embodiments are described herein.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: November 3, 2020
    Assignee: Intel Corporation
    Inventors: Elijah V. Karpov, Prashant Majhi, Ravi Pillarisetty, Uday Shah, James S. Clarke
  • Patent number: 10825741
    Abstract: One illustrative IC product disclosed herein includes an isolation structure that separates a fin into a first fin portion and a second fin portion, an epi semiconductor material positioned on the first fin portion in a source/drain region of a transistor device, wherein a lateral gap is present between a first sidewall of the epi semiconductor material and a second sidewall of the SDB isolation structure, and a conductive source/drain structure that is conductively coupled to the epi semiconductor material, wherein a gap portion of the conductive source/drain structure is positioned in the gap and physically contacts the first sidewall and the second sidewall.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: November 3, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Ruilong Xie
  • Patent number: 10818789
    Abstract: In a transistor region of an active region, trench-gate MOS gates for a vertical MOSFET are formed on the front surface side of a semiconductor substrate. In a non-effective/pad region of the active region, a gate pad is formed on the front surface of the semiconductor substrate with an interlayer insulating film interposed therebetween. An n-type region is formed spanning across the entire non-effective region in the surface layer of the front surface of the semiconductor substrate. The portion directly beneath the gate pad is only an n-type region constituted by an n+ starting substrate, an n? drift region, and the n-type region, with the interlayer insulating film sandwiched thereabove. No n+ source region is formed in a p-type base region extension which is the portion of a p-type base region that extends into the non-effective region.
    Type: Grant
    Filed: July 5, 2019
    Date of Patent: October 27, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Keishirou Kumada, Yasuyuki Hoshi, Yoshihisa Suzuki, Yuichi Hashizume
  • Patent number: 10818515
    Abstract: The present disclosure provides an electronic package and a method for fabricating the same. A protective layer is formed on a carrier of the electronic component. The electronic component and the protective layer are covered by a covering layer. A through hole is formed in the covering layer and extends through the protective layer, such that a portion of a surface of the carrier is exposed to the through hole. A conductive structure is disposed in the through hole and electrically connected with the carrier. Through the formation of the protective layer, the buffering effect of the protective layer can prevent the laser from directly burning through the covering layer and the protective layer to avoid damages to the carrier.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: October 27, 2020
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Yu-Wei Yeh, Yen-Hung Lin, Chih-Yi Liao, Chih-Hsien Chiu
  • Patent number: 10818818
    Abstract: A semiconductor device includes: a first semiconductor region; and a first electrode on the first semiconductor region; wherein first semiconductor region includes a first layer and a second layer, the second layer includes a first portion and a second portion adjacent to the first portion, the first portion has a first thickness, the second portion has a second thickness less than the first thickness, the first layer includes a first material and a first dopant, the first material includes multiple elements, the first dopant has a first concentration, the second layer includes a second material and a second dopant, the second material includes multiple elements, the second dopant has a second concentration, one of the elements of the first material of the first layer is different from the elements of the second material of the second layer.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: October 27, 2020
    Assignee: EPISTAR CORPORATION
    Inventors: Tzu-Chieh Hu, Wei-Chieh Lien, Chen Ou, Chia-Ming Liu, Tzu-Yi Chi
  • Patent number: 10811422
    Abstract: Methods according to the disclosure include forming a mask over a substrate to cover a first semiconductor region on the substrate and a first gate structure on the first semiconductor region. The second semiconductor region may be recessed from an initial height above the substrate to a reduced height above the substrate. The mask may be removed before forming a plurality of cavities by etching the first and second semiconductor regions, the plurality of cavities including a first cavity having a first depth within the first semiconductor region and a second cavity having a second depth within the second semiconductor region, wherein the second depth is greater than the first depth. The method also may include forming a plurality of epitaxial regions within the plurality of cavities.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: October 20, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Yanping Shen, Wei Hong, Hui Zang, David P. Brunco
  • Patent number: 10811432
    Abstract: There is provided with the following semiconductor device to improve its reliability. In a SOI substrate including a semiconductor substrate, an insulating layer, and a semiconductor layer, a diffusion region is formed in the semiconductor layer and a plug electrically connected to the diffusion region is formed on the diffusion region. An element isolation portion is formed within the semiconductor substrate and a trench is formed in the element isolation portion. The lowest part of the bottom of the trench is lower than the surface of the semiconductor substrate and a sidewall spacer is formed in the side portion of the trench to cover the side surface of the insulating layer. As the result, even when the plug is formed in a deviated position, a disadvantage of conducting the semiconductor layer with the semiconductor substrate can be suppressed.
    Type: Grant
    Filed: October 8, 2018
    Date of Patent: October 20, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Nobuo Tsuboi
  • Patent number: 10796946
    Abstract: A method is provided for preparing a semiconductor-on-insulator structure comprising a multilayer dielectric layer.
    Type: Grant
    Filed: October 7, 2019
    Date of Patent: October 6, 2020
    Assignee: SunEdison Semiconductor Limited (UEN201334164H)
    Inventors: Henry Frank Erk, Sasha Kweskin, Jeffrey L. Libbert, Mayank Bulsara
  • Patent number: 10777606
    Abstract: A first memory device includes a first magnetoresistive cell having a plurality of deposition layers. A second memory device includes a second magnetoresistive cell having a plurality of deposition layers. Each of the plurality of deposition layers of the second magnetoresistive cell corresponds to one of the plurality of deposition layers of the first magnetoresistive cell. One of the plurality of deposition layers of the second magnetoresistive cell is thinner than a corresponding deposition layer of the plurality of deposition layers of the first magnetoresistive cell.
    Type: Grant
    Filed: January 15, 2018
    Date of Patent: September 15, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Jae hoon Kim
  • Patent number: 10770576
    Abstract: A MOSFET device is integrated in a body of semiconductor material of a first conductivity type accommodating a body region, of a second conductivity type, and a source region, of the first conductivity type. A gate region extends over the top surface of the body; a source pad extends over the first top surface and is electrically coupled to the source region, a first gate pad extends over the first main surface, alongside the source pad, and is electrically coupled to the gate region; a drain pad extends over the rear surface and is electrically coupled to the body; a second gate pad extends over the rear surface, alongside the drain pad; and a conductive via extends through the body and electrically couples the gate region to the second gate pad.
    Type: Grant
    Filed: October 8, 2018
    Date of Patent: September 8, 2020
    Assignee: STMicroelectronics S.r.l.
    Inventors: Fabio Russo, Cristiano Gianluca Stella