Abstract: A semiconductor package includes a first package component comprising: a first semiconductor die; a first encapsulant around the first semiconductor die; and a first redistribution structure electrically connected to the semiconductor die. The semiconductor package further includes a second package component bonded to the first package component, wherein the second package component comprises a second semiconductor die; a heat spreader between the first semiconductor die and the second package component; and a second encapsulant between the first package component and the second package component, wherein the second encapsulant has a lower thermal conductivity than the heat spreader.

Abstract: A routing structure is disclosed. A first wiring line coupled to a programming access device and a routing block driver and receiver enabling device and a second wiring line coupled to a programming access device and a routing block driver and receiver enabling device. An insulator-metal-transistor device that includes a top electrode, a middle electrode and a bottom electrode, coupled at the intersection of the first wiring line and the second wiring line.

Abstract: A semiconductor package comprises a package substrate, a semiconductor chip on the package substrate, and an interposer substrate on the semiconductor chip. The interposer substrate comprises a first surface facing the semiconductor chip and a trench in the first surface, the trench vertically overlapping the semiconductor chip. An insulating filler is provided between the semiconductor chip and the interposer substrate, and at least partially fills the trench of the interposer substrate.

Abstract: A semiconductor package includes an upper substrate having a first surface and a second surface which are opposite to each other, a lower semiconductor chip disposed on the first surface of the upper substrate, a plurality of conductive pillars disposed on the first surface of the upper substrate at at least one side of the lower semiconductor chip, and an upper semiconductor chip disposed on the second surface of the upper substrate. The lower semiconductor chip and the plurality of conductive pillars are connected to the first surface of the upper substrate, and the upper semiconductor chip is connected to the second surface of the upper substrate.

Abstract: One or more stud bumps may form a conductive column to a component having back side metallization. In an embodiment, the column of stud bumps may be about 130 um vertically (Z-direction). Providing a microelectronics package with a column of stud bumps electrically connected to a component having back side metallization may provide a cost effective electrical interconnect and may enable the incorporation of components of different thicknesses, including that the component thicknesses are independent of each other, in a single fanout package, while providing a thin package profile and back side surface finish integration.

Abstract: A semiconductor package includes a first substrate including a first recess formed in a top surface of the first substrate, a first semiconductor chip disposed in the first recess and mounted on the first substrate, an interposer substrate disposed on the first semiconductor chip and including a second recess formed in a bottom surface of the interposer substrate, an adhesive layer disposed in the second recess and in contact with a top surface of the first semiconductor chip, a plurality of connection terminals spaced apart from the first recess and connecting the first substrate to the interposer substrate, and a molding layer disposed between the first substrate and the interposer substrate.

Abstract: The resent disclosure provides an OLED substrate, a photo mask, and a method of manufacturing the OLED substrate. In one embodiment, an OLED substrate includes: a base substrate; an anode layer on the base substrate; a pixel defining layer on the anode layer, the pixel defining layer having a pattern opening area, the pattern opening area including a plurality of pixel openings arranged in an array manner; and a light-emitting layer formed on the pixel defining layer by evaporation; wherein the pattern opening area has an inward contraction structure with respect to a regular pixel opening area structure in which a plurality of pixel openings are arranged in a manner of an regular array where rows in the regular array are equally spaced from each other and are parallel to each other and columns in the regular array are equally spaced from each other and are parallel to each other.

Abstract: An embodiment package includes a first integrated circuit die, an encapsulant around the first integrated circuit die, and a conductive line electrically connecting a first conductive via to a second conductive via. The conductive line includes a first segment over the first integrated circuit die and having a first lengthwise dimension extending in a first direction and a second segment having a second lengthwise dimension extending in a second direction different than the first direction. The second segment extends over a boundary between the first integrated circuit die and the encapsulant.

Abstract: An interconnect structure may include a graphene-metal barrier on a substrate and a conductive layer on the graphene-metal barrier. The graphene-metal barrier may include a plurality of graphene layers and metal particles on grain boundaries of each graphene layer between the plurality of graphene layers. The metal particles may be formed at a ratio of 1 atom % to 10 atom % with respect to carbon of the plurality of graphene layers.

Abstract: A package structure includes a first package including a first substrate and a first molded portion disposed on the first substrate; and a rigid-flexible substrate disposed on at least a portion of the first package and having a rigid region and a flexible region. The first molded portion is disposed between the first substrate and the rigid-flexible substrate.

Abstract: In one example, an electronic device, comprises a first substrate comprising a first conductive structure, a second substrate comprising a second conductive structure, wherein the first substrate is over the second substrate, a first electronic component between the first substrate and the second substrate, a vertical interconnect between the first substrate and the second substrate, wherein the vertical interconnect is coupled with the first conductive structure and the second conductive structure, and an encapsulant between the first substrate and the second substrate and covering the vertical interconnect. A vertical port on the first electronic component is exposed by an aperture of the first substrate. Other examples and related methods are also disclosed herein.

Abstract: According to an aspect, a multi-chip packaging structure includes a first substrate having a first surface and a second surface, where the first substrate has a conductive layer portion. The multi-chip packaging structure includes an image sensor device coupled to the first surface of the first substrate, a first device coupled to the second surface of the first substrate, and a second substrate disposed apart from the first substrate, where the second substrate has a conductive layer portion. The conductive layer portion of the first substrate is communicatively connected to the conductive layer portion of the second substrate. The first device is disposed between the first substrate and the second substrate. The multi-chip packaging structure includes a second device coupled to the second substrate, and a third device coupled to the first substrate or the second substrate.

Abstract: A semiconductor rectifier includes a transistor and a diode. The transistor includes a source electrode, a drain electrode and a gate electrode. The diode includes an anode electrode and a cathode electrode. The anode electrode is electrically connected to the gate electrode, and the cathode electrode is electrically connected to the source electrode.

Abstract: A jointing material includes: at least one type of element at 0.1 wt % to 30 wt %, the element being capable of forming a compound with each of tin and carbon; and tin at 70 wt % to 99.9 wt % as a main component.

Abstract: A display apparatus includes: a substrate comprising a first display area including a first pixel area, a second pixel area, and a first transmission area, a second display area adjacent to the first display area, the second display area including a third pixel area, a fourth pixel area, a second transmission area, and a third transmission area, and a third display area adjacent to the second display area.

Abstract: A semiconductor device package and method for manufacturing the same are provided. The semiconductor device package includes a first conductive structure, a stress buffering layer and a second conductive structure. The first conductive structure includes a substrate, and a first circuit layer disposed on the substrate. The first circuit layer includes a conductive wiring pattern, and the conductive wiring pattern is an uppermost conductive pattern of the first circuit layer. The stress buffering structure is disposed on the first conductive structure. The second conductive structure is disposed over the stress buffering structure. The conductive wiring pattern extends through the stress buffering structure and electrically connected to the second conductive structure, and an upper surface of the conductive wiring pattern is substantially coplanar with an upper surface of the stress buffering structure.

Abstract: A semiconductor device includes a semiconductor substrate, a dielectric structure, an electrical insulating and thermal conductive layer and a circuit layer. The electrical insulating and thermal conductive layer is disposed over the semiconductor substrate. The dielectric structure is disposed over the electrical insulating and thermal conductive layer, wherein a thermal conductivity of the electrical insulating and thermal conductive layer is substantially greater than a thermal conductivity of the dielectric structure. The circuit layer is disposed in the dielectric structure.

Abstract: A first memory device includes a first magnetoresistive cell having a plurality of deposition layers. A second memory device includes a second magnetoresistive cell having a plurality of deposition layers. Each of the plurality of deposition layers of the second magnetoresistive cell corresponds to one of the plurality of deposition layers of the first magnetoresistive cell. One of the plurality of deposition layers of the second magnetoresistive cell is thinner than a corresponding deposition layer of the plurality of deposition layers of the first magnetoresistive cell.

Abstract: The present disclosure provides a packaged device that includes a first dielectric layer; a second dielectric layer, formed over the first dielectric layer, that includes a device substrate and a via extending from the first dielectric layer and through the second dielectric layer; and a third dielectric layer, formed over the second dielectric layer, that includes a conductive pillar extending through the third dielectric layer, wherein the conductive pillar is electrically coupled to the via of the second dielectric layer.

Abstract: Described herein are techniques related to a semiconductor fabrication process that facilitates the enhancement of systemic conformities of patterns of the fabricated semiconductor wafer. A semiconductor wafer with maximized systemic conformities of patterns will maximize the electrical properties and/or functionality of the electronic devices formed as part of the fabricated semiconductor wafer. This Abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.