Abstract: A lighting system includes one or more methods and systems to control an input switching stage of a power converter to provide power for a lamp and modulate a line current supplied to the power converter to carry data related to a state of the lamp. In at least one embodiment, a single controller consolidates the functions of controlling an input stage of the power converter and communicating to an external device by modulating the line current supplied to the power converter to carry data related to a state of the lamp. The particular type of current modulation and communication protocol utilized by the consolidated power conversion-communication controller is a matter of design choice. In at least one embodiment, the lamp includes one or more electronic light sources, such as one or more light emitting diodes (LEDs) and/or one or more compact fluorescent lamps (CFLs).

Abstract: Techniques and circuits are disclosed for obtaining a physical unclonable function (PUF) circuit that is configured to provide, during a first operational mode, an output signal that is dependent on an electric characteristic of the PUF circuit. Techniques and circuits described herein can cause the PUF circuit to enter a second operational mode by applying a stress signal to the PUF circuit that changes a value of the electric characteristic relative to another value of the electric characteristic during the first operational mode of the PUF circuit; and adjusting, based on changing the absolute value of the first electric characteristic, a bias magnitude of the output signal relative to another bias magnitude of the output signal during the first operational mode of the PUF circuit.

Abstract: State machine engines are disclosed, including those having an instruction insertion register. One such instruction insertion register may provide an initialization instruction, such as to prepare a state machine engine for data analysis. An instruction insertion register may also provide an instruction in an attempt to resolve an error that occurs during operation of a state machine engine. An instruction insertion register may also be used to debug a state machine engine, such as after the state machine experiences a fatal error.

Abstract: An integrated-circuit field-programmable gate array comprising a plurality of arrayed logic elements. The array includes a plurality of first electrical conductors extending along at least portions of the array, and a plurality of second electrical conductors extending along at least portions of the array. The first conductors cross the second conductors at switch cell locations. The first and second conductors are electrically discontinuous at the switch cell locations so that each switch cell is associated with first and second ends of one of the first conductors, and is also associated with first and second ends of one of the second conductors. A plurality of electrical nanotube switches are provided and associated with each of the switch cells.

Abstract: A phase controller includes a plurality of pulse width modulation (PWM) circuits, a plurality of switching devices, a computing unit, and a latency generator. The plurality of PWM circuits output pulse signals. The plurality of switching devices are coupled to the respective plurality of PWM circuits, and switch on and off based on the pulse signals. The computing unit calculates the pulse signals to be output from the plurality of PWM circuits, based on outputs of the plurality of switching devices. The latency generator generates latency in any of the pulse signals so that edge positions of the pulse signals output from the plurality of PWM circuits do not collide with each other, wherein the pulse signals change values at the edge positions.

Abstract: A method for forming a multiplexor integrated circuit includes employing four complementary pairs of vertical field effect transistor (VFET) pairs, each of the complementary pairs of VFETs includes a first VFET device having a gate and a second VFET device having a gate, the gate of the first VFET device is connected to the gate of the second VFET device. The four complementary pairs VFET pairs are arranged to form a signal input portion of the multiplexor with four contact poly pitch (CPP) The plurality source/drain connections are operably connected.

Abstract: A status indicating light unit includes a power input terminal, an illumination circuit, comprising at least one LED, a continuous connection circuit, coupled to the illumination circuit and configured to effect a continuous power transfer from a power input terminal to the illumination circuit, a pulsed power reception circuit, coupled to the illumination circuit and configured to draw power from the power input terminal in a pulsed manner and to continuously emit power to the illumination circuit, and a mode selection switch adapted to couple the continuous connection circuit to the power input terminal in a continuous power draw mode, resulting in a continuous power draw pattern of the status indicating light unit, and adapted to couple the pulsed power reception circuit to the power input terminal in a pulsed power draw mode.

Abstract: A packaged integrated circuit device includes a first driver, which has a first pair of differential output terminals and a first common-mode sensing terminal, and a second driver, which has a second pair of differential output terminals and a second common-mode sensing terminal. The second driver can be a smaller scaled replica of the first driver. A comparator and a reference signal generator are provided. The comparator is configured to compare first and second common-mode voltage signals developed at the first and second common-mode sensing terminals, respectively, and the reference signal generator is configured to provide the first and second drivers with a reference voltage having a magnitude that varies in response to changes in a signal generated at an output terminal of the comparator. This variation in the magnitude of the reference voltage supports a built-in adaptive response to changes in source-side termination in HCSL driver/receiver circuits.

Abstract: A method of synchronizing a driving module includes applying a plurality of original data enable (“DE”) signals to a plurality of timing controller of the driving module, respectively, generating a synch DE signal from the driving module based on the earliest signal among the original DE signals, and transferring the synch DE signal to the plurality of timing controllers in a cascade mode.

Abstract: A device for driving several light sources is provided, wherein the several light sources are arranged in a matrix structure; wherein the several light sources of the matrix structure are connected to a semiconductor device; wherein a portion of the semiconductor device corresponds to a light source of the matrix structure, wherein the portion of the semiconductor device comprises a diagnosis function which when activated is arranged for supplying an output diagnosis signal.

Abstract: A semiconductor device may include a data output circuit and control signal output circuit. The data output circuit may convert a first input signal and a second input signal sequentially inputted thereto into output data and may compare the first and second input signals with a storage datum to generate a first comparison signal and a second comparison signal. The control signal output circuit may detect logic levels of bits included in the first and second comparison signals to generate a first detection signal and a second detection signal, may generate a first flag signal and a second flag signal from the first and second detection signals in response to a storage flag signal, and may sequentially output the first and second flag signals as transmission control signals.

Abstract: A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.

Abstract: Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a programmable logic device (PLD) includes a plurality of programmable logic blocks (PLBs) and a plurality of logic cells within at least one of the PLBs, where each logic cell includes a four input lookup table (4-LUT) configured to provide a 4-LUT output signal to associated carry logic. Each logic cell is configurable according to at least two selectable operational modes including a logic function output mode and a ripple arithmetic output mode, and at least three of the 4-LUT inputs are interchangeable when a selected operational mode comprises the ripple arithmetic output mode.

Abstract: Control methods and apparatuses providing a holding current for a TRIAC dimmer are disclosed. A control method is suitable for a power controller powered by an operation power source. A high-voltage device in the power controller is connected between the operation power source and an input power source, from which the high-voltage device drains a conduction current. An operation voltage of the operation power source is detected, and, during a startup procedure, the conduction current is forwarded to charge the operation power source. A detected voltage representing an input voltage of the input power source is provided, and if the detected voltage is below a setting voltage, the conduction current is forwarded to a ground line instead of charging the operation power source.

Abstract: Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a programmable logic device (PLD) includes a plurality of programmable logic blocks (PLBs) and at least first and second logic cells within at least one of the PLBs, where each logic cell includes a lookup table (LUT) and associated mode logic configured to receive a LUT output signal from the LUT. The associated mode logic is configured to use a single physical signal output to provide a logic cell output signal corresponding to a selected logic function operational mode, ripple arithmetic operational mode, or extended logic function operational mode for each logic cell.

Abstract: A field programmable gate array (“FPGA”) is provided having integrated application specific integrated circuit (“ASIC”) fabric. The ASIC fabric may be used to implement one or more custom or semi-custom hard blocks within the FPGA. The ASIC fabric can be made up of a “custom region” and an “interface region.” The custom region can implement the custom or semi-custom ASIC design and the interface region can integrate and connect the custom region to the rest of the FPGA circuitry. The custom region may be based on a structured ASIC design. The interface region may allow the ASIC fabric to be incorporated within the hierarchical organization of the FPGA, allowing the custom region to connect to the FPGA circuitry in a seamless manner.

Abstract: A semiconductor device includes a first power supply node and a second power supply node having a voltage value higher than the first power supply node. A first switch interrupts a power supplied from the first power supply node to a first circuit node. A second switch interrupts a power supplied from the second power supply node to a second circuit node. A driver drives the second switch by a third switch being driven. The third switch is connected between the second power supply node and the first circuit node. A controller outputs a control signal to drive the first and third switches.

Abstract: There is set forth herein a dimmer circuit for controlling delivery of input line voltage to a load. The dimmer circuit can include a switch coupling an input line voltage terminal to a load terminal. The dimmer circuit can be operative to provide one or more switch firing control scheme for latching the switch.

Abstract: A plasma source includes a first electrode and a second electrode having respective surfaces, and an insulator that is between and in contact with the electrodes. The electrode surfaces and the insulator surface substantially define a plasma cavity. The insulator surface defines one or more grooves configured to prevent deposition of material in a contiguous form on the insulator surface. A method of generating a plasma includes introducing one or more gases into a plasma cavity defined by a first electrode, a surface of an insulator that is in contact with the first electrode, and a second electrode that faces the first electrode. The insulator surface defines one or more grooves where portions of the insulator surface are not exposed to a central region of the cavity. The method further includes providing RF energy across the first and second electrodes to generate the plasma within the cavity.

Abstract: The present disclosure discloses a method based on microcontroller circuit and software codes to on line automatically detect the time phase of the threshold voltage of a lighting load in each AC half-cycle. This automatic detection capability enables a dimmer circuit of a lighting apparatus to establish a dimmer working range from the self-detected time phase of threshold voltage of the lighting load. The lighting apparatus can be operated with different types of lighting loads to perform a full dimming range from 0% to 100% of maximum lighting output. Therefore, the dimmer circuit makes possible both the lighting fixtures and the users refrained from dimming difficulties caused by different types of lighting loads with different threshold voltages. The design concept can be extended to manage illuminations in a two-level security light on a simple software basis without resorting to complex electric circuits.