Abstract: A method of configuring a plurality of configurable integrated circuit dies including receiving a configuration data stream at a die stack. The configuration data stream includes configuration memory data for logic devices located on dies in the die stack. At least two of the dies are located on different substrates. The method also includes, performing for each of the dies in the die stack: receiving the configuration memory data for the die, storing the configuration memory data for the die in a configuration memory on the die, determining whether the configuration data stream includes configuration memory data for an additional die in the die stack, and transmitting the configuration data stream to the additional die in the die stack in response to the configuration data stream including configuration memory data for the additional die in the die stack.

Abstract: Apparatuses and methods are disclosed, including an apparatus that includes a first differential amplifier to amplify a difference between an input signal and a reference signal, and a second differential amplifier to amplify the difference between the input signal and the reference signal. The apparatus may further include an inverter circuit to receive an output signal of the first differential amplifier and another inverter circuit to receive an output signal of the second differential amplifier. The apparatus may include an output circuit to combine the outputs of the inverter circuits. The inverter circuits may each include an inverter and a shunt resistance. Additional apparatuses and methods are described.

Abstract: It is desirable to design and manufacture electronic chips that are resistant to modern reverse engineering techniques. Disclosed is a method and device that allows for the design of chips that are difficult to reverse engineer using modern teardown techniques. The disclosed device uses devices having the same geometry but different voltage levels to create different logic devices. Alternatively, the disclosed uses devices having different geometries and the same operating characteristics. Also disclosed is a method of designing a chip using these devices.

Abstract: An LED lamp has two preheating current control units respectively connected to a first electrode terminal and a second electrode terminal of the LED lamp, two lamp-side rectification circuits, and an LED light string. Each preheating current control unit has a ballast-side rectification circuit connected to one of the first and second electrode terminals and a load-varying circuit having a resistive load and a control circuit. The resistive load is serially connected to a DC output terminal of the ballast-side rectification circuit through the control circuit. The control circuit adjusts a resistance of the resistive load. Two input terminals of each lamp-side rectification circuit are respectively connected to one of the electrodes of each of the first electrode terminal and the second electrode terminal. The LED light string has two ends respectively connected to the two output terminals of each lamp-side rectification circuit, and has multiple series-connected LED elements.

Abstract: A method for enabling double pumping in a limited switch dynamic logic circuit includes precharging a dynamic node in accordance with a first clock signal and a second clock signal. The dynamic node is evaluated to a first value in response to one or more first input signals of a first evaluation tree in accordance with the first clock signal. The dynamic node is evaluated to a second value in response to one or more second input signals of a second evaluation tree in accordance with the second clock signal.

Abstract: A LED driving apparatus and an operating method thereof are disclosed. The LED driving apparatus includes a power, at least one LED string, a LED control unit, and an input voltage detection circuit. At least one LED string is coupled to the power and includes LEDs connected in series. The input voltage detection circuit is coupled to two ends of at least one LED of the LEDs respectively and used to judge whether an input voltage is lower than a LED conducting voltage. The input voltage detection circuit includes a charging capacitance to be charged when the at least one LED string is conducted. If the judged result of the input voltage detection circuit is yes, the input voltage detection circuit will control the charging capacitance having a charging voltage to discharge to the at least one LED string.

Abstract: A dynamic logic circuit includes a precharge device configured to precharge a dynamic node in accordance with a first and second evaluation clock signal. A first evaluation tree is configured to evaluate the dynamic node to a first value in response to one or more first input signals in accordance with the first evaluation clock signal. A second evaluation tree configured to evaluate the dynamic node to a second value in response to one or more second input signals in accordance with the second evaluation clock signal.

Abstract: A logic circuit includes a thin film transistor having a channel formation region formed using an oxide semiconductor, and a capacitor having terminals one of which is brought into a floating state by turning off the thin film transistor. The oxide semiconductor has a hydrogen concentration of 5×1019 (atoms/cm3) or less and thus substantially serves as an insulator in a state where an electric field is not generated. Therefore, off-state current of a thin film transistor can be reduced, leading to suppressing the leakage of electric charge stored in a capacitor, through the thin film transistor. Accordingly, a malfunction of the logic circuit can be prevented. Further, the excessive amount of current which flows in the logic circuit can be reduced through the reduction of off-state current of the thin film transistor, resulting in low power consumption of the logic circuit.

Abstract: A device including first and second semiconductor chips, each of first and second semiconductor chips including first to M-th penetration electrodes, M being an integer equal to or greater than 3, each of the first to M-th penetration electrodes penetrating through a semiconductor substrate, and the first semiconductor chip including a first input circuit coupled to the M-th penetration electrode of the first semiconductor chip at an input node thereof, the first and second semiconductor chips being stacked with each other in which the first to M-th penetration electrodes of the second semiconductor chip are vertically arranged respectively with the first to M-th penetration electrodes of the first semiconductor chip, in which the first to (M?2)-th penetration electrodes of the second semiconductor chip are electrically coupled to the second to (M?1)-th penetration electrodes of the first semiconductor chip, respectively.

Abstract: A semiconductor device in which operation delay due to stop and restart of the supply of a power supply potential is suppressed is provided. Potentials corresponding to data held in first and second nodes while the supply of a power supply potential is continued are backed up in third and fourth nodes while the supply of the power supply potential is stopped. After the supply of the power supply potential is restarted, data are restored to the first and second nodes by utilizing a change in channel resistance of a transistor whose gate is electrically connected to the third or fourth node. Note that shoot-through current is suppressed at the time of data restoration by electrically disconnecting the power supply potential and the first or second node from each other.

Abstract: An implementation method for a fast Null Convention Logic (NCL) data path includes a pipeline that is assembled from gates of various types of NCL. Self-ready flash NCL gates include a one-shot circuit to reset the gates to a null state and prepare the gates for the next wave of asserted data. In one embodiment, the one-shot circuit creates a flash pulse inside a gate in response to a change of a flash input line and ends the flash pulse in response to the gate output being reset to a null state. Conventional logic can be included in the data path as well.

Abstract: A current controller 42 compares a first coil current IL1 flowing in an output inductor L1 with a first upper threshold value and a first lower threshold value. A current limiter 44 compares a second coil current IL2 flowing in an input inductor L2 with a second upper threshold value and a second lower threshold value. A duty controller 46 (i) switches a switching transistor M1 based on the first coil current in a cycle where the first coil current IL1 exceeds the first upper threshold value before the second coil current IL2, exceeds the second upper threshold value. According to the current controller 42, it is possible to stabilize an output current and to limit a current.

Abstract: Providing for a field programmable gate array (FPGA) utilizing resistive random access memory (RRAM) technology is described herein. By way of example, the FPGA can comprise a switching block interconnect having parallel signal input lines crossed by perpendicular signal output lines. RRAM memory cells can be formed at respective intersections of the signal input lines and signal output lines. The RRAM memory cell can include a voltage divider comprising multiple programmable resistive elements arranged electrically in series across a VCC and VSS of the FPGA. A common node of the voltage divider drives a gate of a pass gate transistor configured to activate or deactivate the intersection. The disclosed RRAM memory can provide high transistor density, high logic utilization, fast programming speed, radiation immunity, fast power up and significant benefits for FPGA technology.

Abstract: A system and method for producing white light in an adjustable light emitting diode (LED) illumination device is provided. The system and method varies the “off” time for one of multiple sets of light emitting diodes (LEDs) or channels in succession in order to compensate for and stabilize the color-shifting or degradation that gradually occurs in LEDs. Each channel corresponds to a different color. By varying the “off” time of only one channel at a time, the system efficiently utilizes the majority of the LEDs, thereby enabling the production of a more stable white light with fewer LEDs.

Abstract: In various embodiments, there is provided a method comprising receiving a waveform; rectifying the waveform to generate a rectified waveform; comparing the rectified waveform with a first voltage to generate a first compare signal, wherein a first edge of the first compare signal occurs at a first time when an instantaneous value of the rectified waveform becomes higher than the first voltage; comparing the rectified waveform with a second voltage to generate a second compare signal, wherein a first edge of the second compare signal occurs at a second time when the instantaneous value of the rectified waveform becomes higher than the second voltage; and based at least in part on the first time and the second time, estimating a voltage of the waveform.

Abstract: A semiconductor apparatus according to the present invention includes a circuit including a predetermined function, a clock generating circuit that generates a clock signal supplied to the circuit, a clock control circuit that controls the clock generating circuit, and a notification signal generating circuit that generates a notification signal for notifying a timing for the clock control circuit to control the clock generating circuit. A voltage supplied to the semiconductor apparatus is adjusted according to the notification signal.

Abstract: Systems and methods for preventing saturation of analog integrator outputs are provided. Applications of the systems and methods in hybrid analog-digital integrators are also provided. Exemplary systems include two switches, one operational amplifier, one capacitor C, four gain blocks, three comparators, one XOR gate, one OR gate, one T flip-flop, and one digital counter.

Abstract: A low power sub-cycle reconfigurable conduit is provided. The low power reconfigurable conduit is a clocked storage element that consumes less power when performing low-throughput operations that do not require sub-cycle rate. The low power conduit includes a first configurable routing multiplexer that is reconfigurable to select one of several inputs at a first clock rate. The low power conduit also includes an array of storage elements for storing output data from the configurable routing multiplexer at the first clock rate. Each storage element in the array of storage elements operate at a second clock rate that is slower than the first clock rate. Each storage element receives a different phase of a clock that operates at the second clock rate. The low power conduit also includes a second configurable routing multiplexer that is reconfigurable to select from the array of storage elements at the first clock rate.

Abstract: A lighting system provides for control of the perceived color of the light emitted by the light fixture. The light fixture has two light sources, a control circuit pulses the two light sources and changes relative duty cycles of the light sources to alter a perceived color output of the lighting fixture, in response to a control signal. Duty cycles of the light sources are a function of the control signal.

Abstract: The present invention provides an LED backlight drive circuit, which includes a first power supply module, an electrical inductor, a rectifier diode, a MOS transistor, an electrolytic capacitor, an LED light string, a voltage division module, a voltage comparator, a second power supply module, and an LED constant-current drive chip. The LED backlight drive circuit is arranged to include a voltage comparator in an external circuit of the LED constant-current drive chip to detect output voltage of the drive circuit so that high voltage, the voltage comparator is caused to supply a low voltage level to forcibly pull down a PWM dimming signal or an ENA enabling signal of the LED constant-current drive chip to achieve an over-voltage protection function and also enable removal of over-voltage protection module from a conventional LED constant-current drive chip.