Patents Examined by Nghia M. Doan
  • Patent number: 10970441
    Abstract: A neural network based learning system for designing a circuit, the design system including at least one memory, at least one processor in communication with said at least one memory, said at least one processor configured to generate a mathematical model of the circuit, determine a structural definition of the circuit from the mathematical model, define a mapping of a plurality of components of the circuit to a plurality of neurons representing the plurality of components of the circuit using at least the structural definition, synthesize, on a hardware substrate, the plurality of neurons, and execute, using the synthesized plurality of neurons on the hardware substrate, at least one test using at least one optimization constraint to determine an optimal arrangement of the plurality of components.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: April 6, 2021
    Assignee: Washington University
    Inventors: Xuan Zhang, Ayan Chakrabarti
  • Patent number: 10973115
    Abstract: A printed circuit board includes a spread weave of fibers having a first direction and a second direction with corresponding fibers spread more in the first direction than the second direction; and one or more pairs of traces on the spread weave of fibers, wherein the first direction has less differences in dielectric permittivity seen by each trace than the second direction, wherein the one or more pairs of traces are routed according to a routing design that includes one or more fixed regions on the spread weave of fibers, where routing of traces therein is restricted to linear, non-angled routed in the first direction.
    Type: Grant
    Filed: August 2, 2019
    Date of Patent: April 6, 2021
    Assignee: Ciena Corporation
    Inventors: Robert Bisson, Marko Antonic
  • Patent number: 10963613
    Abstract: Partial reconfiguration of a programmable integrated circuit can include loading, using computer hardware, a platform design including a module black-box instance corresponding to a user design and marking, using the computer hardware, data of the platform design including data relating to synchronous boundary crossings between the platform design and the module black-box instance and implementation data for the platform design within an extended routing region available for routing the user design. Unmarked data can be removed from the platform design resulting in a shell circuit design. The user design can be implemented based on the shell circuit design and timing constraints corresponding to the marked data in the shell circuit design.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: March 30, 2021
    Assignee: Xilinx, Inc.
    Inventors: Meiwei Wu, Jun Liu, Raymond Kong
  • Patent number: 10965145
    Abstract: A charge control device for controlling charging of a secondary battery by using a current limit function of an external power supply includes: a charge control element arranged to be connected in series between the external power supply and the secondary battery; a constant current control unit configured to control an output current of the charge control element to be constant; a constant voltage control unit configured to control an output voltage of the charge control element to be constant; and an ON state setting unit configured to set the charge control element to an ON state, wherein the charge control element includes a control terminal to which a control signal for controlling the output current and the output voltage is input, and is composed of a single output element.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: March 30, 2021
    Assignee: MITSUMI ELECTRIC CO., LTD.
    Inventors: Daisuke Suzuki, Takafumi Goto, Kensuke Kuroda
  • Patent number: 10956640
    Abstract: The present disclosure relates to a method for electronic design verification. Embodiments may include receiving, using a processor, an electronic design and providing at least a portion of the electronic design to a machine learning engine. Embodiments may further include automatically determining, based upon, at least in part, an output of the machine learning engine whether or not the at least a portion of the electronic design is amenable to formal verification.
    Type: Grant
    Filed: July 10, 2019
    Date of Patent: March 23, 2021
    Assignee: Cadence Design Systems, Inc.
    Inventors: Georgia Penido Safe, Mirlaine Aparecida Crepalde, Yumi Monma, Felipe Althoff, Fernanda Augusta Braga, Lucas Martins Chaves, Pedro Bruno Neri Silva, Mariana Ferreira Marques, Vincent Gregory Reynolds
  • Patent number: 10950903
    Abstract: An electrical system includes a battery pack, sensors, and a controller. The sensors configured output measured state signals indicative of an actual state of the battery back, including a respective actual voltage, current, and temperature of each of the multiple battery cells. The controller executes a method to generate, responsive to the measured state signals, an estimated state of the multiple battery cells using a respective open-circuit voltage and low-frequency transient voltage of each of the multiple battery cells. The controller estimates the low-frequency transient voltages using a porous electrode transient (PET) model as part of a model set, the PET model having open-circuit voltage elements representing uneven charge distribution within a cell electrode. State of charge (SOC) of the battery pack is estimated using the estimated voltages. An operating state of the electrical system is controlled in real-time responsive to the estimated SOC.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: March 16, 2021
    Assignee: GM Global Technology Operations LLC
    Inventors: Charles W. Wampler, II, Daniel R. Baker
  • Patent number: 10949599
    Abstract: In one embodiment, a computer-implemented method includes performing retiming using a first circuit design to determine one or more variations to the first circuit design, identifying one or more source registers that are involved in one or more unsuccessful retiming moves due to initial conditions conflicts, and recommending, via a graphical user interface, one or more corrective actions to the one or more source registers to avoid the initial conditions conflicts and improve performance of the one or more variations.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: March 16, 2021
    Assignee: Altera Corporation
    Inventors: Dai Le, Scott James Brissenden
  • Patent number: 10933519
    Abstract: An electronic torque wrench system comprises a plurality of wrenches (11) which communicate with NFC (Near Field Communication) units (12, 42, 44) connected to a unit (20) for managing the plurality of wrenches. The wrench (11) and the external NFC unit (12, 42, 44) each comprise an NFC module (18, 19) for data exchange between wrench and external unit when the wrench is moved close to the external unit. A recharging base, a system and a method for managing the wrenches are also described.
    Type: Grant
    Filed: June 12, 2017
    Date of Patent: March 2, 2021
    Assignee: SCS CONCEPT S.R.L.
    Inventors: Marco Angelo Cabrel, Roberto Boccellato
  • Patent number: 10929583
    Abstract: Methods and systems for verifying a derived clock using assertion-based verification. The method comprises counting the number of full or half cycles of a fast clock that occur between the rising edge and the falling edge of a slow clock (i.e. during the ON phase of the slow clock); counting the number of full or half cycles of the fast clock that occur between the falling edge and the rising edge of the slow clock (i.e. during the OFF phase of the slow clock); and verifying the counts using assertion-based verification.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: February 23, 2021
    Assignee: Imagination Technologies Limited
    Inventor: Ashish Darbari
  • Patent number: 10915685
    Abstract: The present embodiments relate to static timing analysis (STA) of circuits. The STA can include determining graph based analysis (GBA) delays of timing paths within the circuit. Path based analysis (PBA) delays of a subset of timing paths can be determined to generate circuit stage credit values for circuit stages in the circuit. The circuit stage credit values can be used to adjust GBA delays of the timing paths. Prediction functions can be utilized to predict or estimate PBA delays of timing paths thereby avoiding the determination of actual PBA delays of the timing paths.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: February 9, 2021
    Assignee: Cadence Design Systems, Inc.
    Inventors: Umesh Gupta, Naresh Kumar, Rakesh Agarwal, Sukriti Khanna, Jayant Sharma, Ritika Govila
  • Patent number: 10909300
    Abstract: A customizable routing system allows designers to create custom connection layouts that can be stored, turned into templates, reused, and further customized. The system describes designer-input custom connection layouts in terms of “structural directives” that specify its patterns and properties instead of using precise dimensions. Structural directives may describe particular connection patterns between structural components (e.g., backbone or fishbone), the placement, width, direction or layer of specific structural components, and properties of structural components relative to other components. These structural directives are implemented generally during routing, such as through design constraints, which allows the router to locally optimize the design (e.g., for cost or wire length) while considering the structural intentions of the designer.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: February 2, 2021
    Assignee: Synopsys, Inc.
    Inventors: Hsiang-Wen Jimmy Lin, Friedrich Gunter Kurt Sendig, Mathieu Eric Drut, Philippe Aubert McComber
  • Patent number: 10897144
    Abstract: An apparatus has connectors to receive batteries. A power multiplexer is connected to the connectors. A processor is connected to the power multiplexer to execute a battery charge protocol including the operations of selecting at least one battery for charging, where the at least one battery is in a fast charge state that allows for substantially linear charge performance. Direct current is applied to the battery until the fast charge state is terminated. The selecting and applying operations are repeated until the fast charge state is terminated in each of the batteries. Direct current is then directed to the batteries until a full charge state is reached for each of the batteries.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: January 19, 2021
    Assignee: AMPL LABS, INC.
    Inventors: Michael Patton, Keith Resch, Rafael Calderon, Tomoko Nishioka-Patton
  • Patent number: 10896277
    Abstract: In the described examples, an electronic design automation formal verification EDA application is configured to receive an initial evaluation of a circuit design of an integrated circuit (IC) chip. The circuit design of the IC chip includes a list of properties for the IC chip, and the list of properties includes a list of assertions for the IC chip. The formal verification EDA program extracts a counter-example trace from the initial evaluation. The counter-example trace characterizes a set of signals over a plurality of cycles that reach a state in which a given assertion in the list of assertions does not hold true. The formal verification EDA program identifies a subset of signals in the counter-example trace that remain in a specific constant value over the plurality of cycles. The formal verification EDA program executes an over-constrained formal verification for the circuit design.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: January 19, 2021
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventor: Mike Pedneau
  • Patent number: 10896280
    Abstract: Systems and methods are described for creating a netlist abstraction that provides full-chip context for performing circuit design floorplanning. The netlist abstraction can include a top-level netlist abstraction that corresponds to the top-level portion of the netlist, and a physical block netlist abstraction for each physical block in the circuit design. Each physical block netlist abstraction can retain macros that are in the physical block.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: January 19, 2021
    Assignee: Synopsys, Inc.
    Inventors: Balkrishna R. Rashingkar, Leonardos J. van Bokhoven, Peiqing Zou
  • Patent number: 10878163
    Abstract: A semiconductor structure includes a power grid layer (including a first metallization layer) and a set of cells. The first metallization layer includes: conductive first and second portions which provide correspondingly a power-supply voltage and a reference voltage, and which have corresponding long axes oriented substantially parallel to a first direction; and conductive third and fourth portions which provide correspondingly the power-supply voltage and the reference voltage, and which have corresponding long axes oriented substantially parallel to a second direction substantially perpendicular to the first direction. The set of cells is located below the PG layer. Each cell lacks a conductive structure which is included in the first metallization layer. The cells are arranged to overlap at least one of the first and second portions in a repeating relationship with respect to at least one of the first or second portions of the first metallization layer.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: December 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hiranmay Biswas, Chung-Hsing Wang, Kuo-Nan Yang
  • Patent number: 10878164
    Abstract: Disclosed are methods, systems, and articles of manufacture for probing a multi-fabric electronic design that spans across multiple design fabrics. These techniques identify a single layout editor, a first electronic design in a first design fabric, and a second electronic design in a second design fabric. An input for probing a circuit component in the first electronic design may further be identified at a user interface of a computing system. The circuit component being probed is connected to an instance of the second electronic design. In response to the input, one or more co-design modules render a representation of the first layout with emphasized circuit components in the first design fabric and the second design fabric, wherein the one or more co-design modules are stored at least partially in memory of and function in conjunction with at least one microprocessor of a computing system.
    Type: Grant
    Filed: October 10, 2018
    Date of Patent: December 29, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventor: Arnold Jean Marie Gustave Ginetti
  • Patent number: 10872185
    Abstract: Example systems and methods are disclosed for estimating wire capacitance in an RTL circuit design. In an embodiment, a reference post-layout design is received from a non-transitory storage medium, and gate-level nets within the reference post-layout design are classified as either long nets or short nets based, at least in part, on an average fanout length within the gate-level net. A parasitic model may be generated for each of the gate-level nets, and the gate-level nets and associated parasitic models may be stored within either a long net database or a short net database based on the classification of the gate-level net. A net from the RTL circuit design may be classified as either long or short based, at least in part, on a number of modules crossed by one or more fanouts within the net. If the net from the RTL circuit design is classified as long, then capacitance for the net may be estimated using a parasitic model selected from the long net database.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: December 22, 2020
    Assignee: Ansys, Inc.
    Inventors: Seema Naswa, Praveen Singhal, Paul Traynar
  • Patent number: 10872192
    Abstract: Disclosed are methods, systems, and articles of manufacture for reducing interferences and disturbances in a multi-fabric electronic design. These techniques identify connectivity for an electronic design that includes design data in multiple design fabrics. One or more interference modules are executed to detect a loop in the electronic design with at least the connectivity. These techniques further execute the one or more interference reduction modules to determine at least one critical circuit component upon which the loop exerts a negative impact. One or more remedial actions are then triggered to reduce or eliminate the negative impact on the critical circuit component design.
    Type: Grant
    Filed: October 10, 2018
    Date of Patent: December 22, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventors: Arnold Jean Marie Gustave Ginetti, Jean-Noel Pic
  • Patent number: 10867090
    Abstract: A method for designing a system on a target device is disclosed. The system is synthesized from a register transfer level description. The system is placed on the target device. The system is routed on the target device. A configuration file is generated that reflects the synthesizing, placing, and routing of the system for programming the target device. A modification for the system is identified. The configuration file is modified to effectuate the modification for the system without changing the placing and routing of the system.
    Type: Grant
    Filed: March 18, 2019
    Date of Patent: December 15, 2020
    Assignee: Intel Corporation
    Inventors: Gregg William Baeckler, Martin Langhammer, Sergey Gribok, Scott J. Weber, Gregory Steinke
  • Patent number: 10867093
    Abstract: Disclosed approaches for guiding actions in processing a circuit design include a design tool identifying first violations of design checks and determining severity levels of the first violations. The design tool determines for each violation, suggested actions associated with the violation and presents on a display, first data indicative of the suggested actions in order of the severity levels of the first violations. The first data include selectable objects, and each selectable object has an associated executable procedure. The design tool can execute the procedure associated with one of the selectable objects in response to selection and modify the circuit design in response to execution of the procedure.
    Type: Grant
    Filed: March 20, 2019
    Date of Patent: December 15, 2020
    Assignee: Xilinx, Inc.
    Inventors: John Blaine, Srinivasan Dasasathyan, Meghraj Kalase, Frederic Revenu, Veeresh Pratap Singh, Satish Bachina, Shail Bains, Padmini Gopalakrishnan, Sumit Nagpal, Gaurav Dutt Sharma