Abstract: A battery pack includes at least one battery module including a plurality of battery cells, and a module housing to receive the plurality of battery cells, at least one thermoelectric module disposed outside or inside of the module housing of the battery module and configured to generate voltage when a temperature of the battery module rises to a predetermined temperature or above, and an energy drain unit configured to discharge the battery module when a predetermined magnitude of voltage or above is applied from the thermoelectric module.

Abstract: A photonic element for a quantum information processing device contains a high-purity silicon layer. The high-purity silicon layer contains integrated rare-earth element (REE) dopants at a concentration of 1019 cm?3 or less. An optical transition between the lowest crystal field levels of the REE dopants integrated in the high-purity silicon layer exhibits a homogeneous linewidth of 1 MHz or less at a temperature of 4 K or less. A method for producing such a photonic element is also disclosed.

Abstract: Aspects of the present disclosure relate generally to systems and methods for use in the implementation and/or operation of quantum information processing (QIP) systems. Coherent optical manipulations in such QIP systems may require interferometric stability between the incident laser beams and the atomic-based qubit (or other type of qubit) being addressed. Mechanical vibrations that affect the position of the qubit with respect to the incident laser beams directly contribute to optical phase differences and reduce fidelity. A technique is described herein that is used to mitigate or reduce optical phase differences arising from vibrations of the qubits with respect to the incident laser beams. This technique is generally applicable to any condition that results in such vibrations and systems needing interferometric stability and is compatible with cryogenic environments.

Abstract: A method includes identifying a cell in the layout diagram as a violated cell that fails to pass one or more design rules related to IR drops, and classifying a root cause of the violated cell with a root cause class. The method also includes determining a searching area for searching safe region candidates, and finding a selected cell for moving based upon the root cause class of the root cause. The method further includes finding a safe region in the searching area for moving the selected cell, and moving the selected cell to the safe region if the safe region is found within the searching area.

Abstract: A method of determining a contribution of a process feature to the performance of a process of patterning substrates. The method may include obtaining a first model trained on first process data and first performance data. One or more substrates may be identified based on a quality of prediction of the first model when applied to process data associated with the one or more substrates. A second model may be trained on second process data and second performance data associated with the identified one or more substrates. The second model may be used to determine the contribution of a process feature of the second process data to the second performance data associated with the one or more substrates.

Abstract: The general field of the disclosure herein relates to the design of one or more health related monitoring or maintenance devices. These devices may include but are not limited to devices that monitor and/or maintain the health of users or devices that monitor and/or maintain the health of assets. The devices include oral cleaning devices for maintaining and monitoring the oral health of users, clothing for monitoring the health and fitness of users and charging pads which may monitor the health or assets being charged. Sensors may be integrated in these devices including but not limited to IMUs, thermocouples or oral cleaning devices, IMUs in clothing like shoes or wrist bands, or timers or charging sensors in magnetic surfaces which may cause one or more objects and/or other magnetic surfaces to float when a desired function is achieved.

Abstract: Technology to map classical data into quantum bits includes generating a set of complex feature vectors based upon a set of classical digital data; converting the complex feature vectors to a complex wave via wave expansion, the complex wave providing a feature representation in a transformed domain, and generating quantum vectors based on the complex wave, wherein the quantum vectors are to be submitted to a quantum computing device. Generating a set of complex feature vectors can include selecting a sequence of data points from the classical digital data and transforming the sequence of data points into a frequency domain. Generating quantum vectors can include determining vector coordinates for each of the quantum vectors. Each of the quantum vectors can be defined by a respective pair of parameters, where submitting the quantum vectors to a quantum computing device includes submitting each respective pair of parameters to the quantum computing device.

Abstract: A method for programming an FPGA, wherein a library, which includes elementary operations and a particular latency table for each of the elementary operations of the library is provided. Each latency table indicates the latency of the particular operation for a plurality of clock rates of the FPGA and for a plurality of input bit widths of the particular operation during the execution on the FPGA, depending on the input bit width of the particular operation and the clock rate of the FPGA. A data path indicating a consecutive execution of at least two elementary operations of the library on the FPGA is defined. The latencies given for the particular input bit width of the particular elementary operations of the data path for a plurality of different clock rates in the latency tables are detected and added, then one of the clock rates is selected.

Abstract: A method of determining a parameter of a patterning process, the method including: obtaining a detected representation of radiation redirected by a structure having geometric symmetry at a nominal physical configuration, wherein the detected representation of the radiation was obtained by illuminating a substrate with a radiation beam such that a beam spot on the substrate was filled with the structure; and determining, by a hardware computer system, a value of the patterning process parameter based on optical characteristic values from an asymmetric optical characteristic distribution portion of the detected radiation representation with higher weight than another portion of the detected radiation representation, the asymmetric optical characteristic distribution arising from a different physical configuration of the structure than the nominal physical configuration.

Abstract: The present disclosure disclosed a wireless charging module manufacturing method. The method includes the following steps: forming a first heat dissipating layer on a surface of a coil; and securing a magnetic shield part to the surface of the coil away from the first heat dissipating layer. A wireless charging module is manufactured by the method. By completely cover the coil with the first heat dissipating layer in the present disclosure, the first heat dissipating layer possesses excellent heat radiation, effectively improving the heat dissipation of the coil. The thickness of the first heat dissipating layer is controllable. Therefore, an effective and highly stable heat dissipating performance can be provided without increasing the thickness and cost of the wireless charging module.

Abstract: A method for optimizing a quantum circuit includes obtaining a quantum circuit model comprising one or more quantum operations, wherein at least one quantum operation is marked as having permutable input registers. An optimization goal for the quantum circuit is determined. A processor selects a permutation of the input registers for the at least one marked quantum operation based on the optimization goal. An optimized quantum circuit is generated based on the selected permutation. The method may further include providing the generated optimized quantum circuit for execution by a quantum execution platform.

Abstract: One or more systems, devices and/or methods of use provided herein relate to a device that can facilitate reduction of inter-qubit cross talk and/or allow for increased interaction strengths between qubits as compared to existing technologies. A device can comprise a qubit lattice comprising a plurality of repeated and connected unit cells, and the unit cells comprising individual sets of qubits, wherein the unit cells comprise different cross talk groups of qubits having qubit islands connected together by couplers in different orders, and wherein the different cross talk groups are repeated among the unit cells of the qubit lattice. A device can comprise a qubit lattice comprising a plurality of different, interconnected cross talk groups of qubits, wherein the different cross talk groups are repeated within the qubit lattice.

Abstract: Embodiments of the present disclosure relate to the field of semiconductors, and provide a process recipe, a method and a system for generating same, and a semiconductor manufacturing method. The method for generating a diffraction-based process recipe includes: providing a basic process recipe, the basic process recipe is used to form an initial alignment pattern; and performing a feedback correction step for at least one time to adjust the basic process recipe and obtain an actual process recipe, which each time includes: obtaining a first pattern and a second pattern based on the basic process recipe prior to a current feedback correction step, the first pattern is the initial alignment pattern that is developed, the second pattern is the initial alignment pattern that is etched; and adjusting the basic process recipe prior to the current feedback correction step based on a difference between the first pattern and the second pattern.

Abstract: A method of making an integrated circuit includes dividing, in a first layer of an integrated circuit layout, a first arrangement of metal lines into a first set of metal lines and a second set of metal lines, wherein the first set of metal lines is between the second set of metal lines and a periphery of the integrated circuit layout, wherein the first arrangement of metal lines is configured to electrically connect to a plurality of contacts connected to a second layer of the integrated circuit layout after a manufacturing process. The method further includes adjusting a metal line perimeter of at least one metal line in the second set of metal lines to make a second arrangement of metal lines, wherein each adjusted metal line perimeter is separated from contacts in the second layer of the integrated circuit layout by at least a check distance.

Abstract: A vehicle power supply system (100), comprising: —a vehicle battery (111) with a charging voltage, —a DC-to-DC converter (130) comprising two first connection terminals (110) connected to the vehicle battery (111) and two second connection terminals (120) for connecting an external charger to recharge the vehicle battery (111) or for connecting an external battery to be recharged, wherein, in a first mode in which an external charger is connected to the two second connection terminals (120), the voltage V2 between the two second connection terminals (120) is an input voltage of the converter and the voltage V1 between the two first connection terminals (110) is an output voltage of the converter, wherein, in a second mode in which an external battery to be recharged is connected to the two second connection terminals (120), the voltage V1 between the two first connection terminals (110) is an input voltage of the converter and the voltage V2 between the two second connection terminals (120) is an output volta

Abstract: A charging cable includes a ground conductor and extending in a longitudinal direction, at least two heavy-current power wires for conducting positive and negative direct current, each comprising a power conductor and insulation, the heavy-current power wires extending parallel to the ground wire, a liquid tight inner sheath extending in the longitudinal direction and surrounding the heavy-current power wires to define a first hollow area between and around the heavy-current power wires, liquid coolant being provided between the heavy-current power wires along the longitudinal direction, wherein the liquid tight inner sheath comprises a second hollow area extending in the longitudinal direction, arranged adjacent to at least one of the heavy-current power wires and comprising liquid coolant to flow within the second hollow area, and a liquid tight outer sheath extending in the longitudinal direction and surrounding the inner sheath and the ground heavy-current wire.

Abstract: Boundary cells may be provided. A boundary of a first functional cell of a circuit is determined. A first plurality of a first type of dummy cells are placed along a first portion of the determined boundary. The first portion extends in a first direction. Each of the first type of dummy cells comprises first pre-defined dimensions. A second plurality of a second type of dummy cells are placed along a second portion of the determined boundary. The second portion extends in a second direction. Each of the second type of dummy cells comprises second pre-defined dimensions. The second pre-defined dimensions is different than the first pre-defined dimensions.

Abstract: Techniques relating to synthesizing masks for use in manufacturing a semiconductor device are disclosed. These techniques include providing, by a processor, a design pattern for a semiconductor device as input to a trained machine learning (ML) model. The techniques further include performing, using the ML Model, a plurality of dilated convolutions relating to the design pattern, and inferring, using the ML model, one or more masks for use in manufacturing the semiconductor device, based on the plurality of dilated convolutions.

Abstract: Disclosed are embodiments of a computer-aided design system and corresponding method for power-optimized timing closure of an integrated circuit (IC) design. In the embodiments, a cell library includes sets of cells, where each cell in the same set has the same internal structure but different combinations of cell boundary isolation structures associated with different passive delay values. Timing closure includes replacement of a cell in a previously generated layout with another cell from the same set in order to adjust delay (e.g., increase delay) of a data signal or clock signal and, thereby facilitate fixing of a previously identified violation of a timing constraint. By eliminating or at least minimizing the need to insert buffer and/or inverter cells into a layout to add delay to a data signal and/or a clock signal during timing closure, the embodiments avoid or at least limit concurrent increases in power consumption and area consumption.

Abstract: Various embodiments of the present technology may provide methods and system for a battery. The system may provide a fuel gauge circuit configured to select an energy curve from a plurality of energy curves and determine a remaining energy value based on the selected energy curve and a computed remaining capacity of the battery. The fuel gauge circuit controls a current to a load based on the remaining energy value.