Patents Examined by Nghia M. Doan
  • Patent number: 11874605
    Abstract: Metrology target design methods and verification targets are provided. Methods comprise using OCD data related to designed metrology target(s) as an estimation of a discrepancy between a target model and a corresponding actual target on a wafer, and adjusting a metrology target design model to compensate for the estimated discrepancy. The dedicated verification targets may comprise overlay target features and be size optimized to be measureable by an OCD sensor, to enable compensation for inaccuracies resulting from production process variation. Methods also comprise modifications to workflows between manufacturers and metrology vendors which provide enable higher fidelity metrology target design models and ultimately higher accuracy of metrology measurements.
    Type: Grant
    Filed: July 6, 2020
    Date of Patent: January 16, 2024
    Assignee: KLA Corporation
    Inventors: Michael E. Adel, Inna Tarshish-Shapir, Shiming Wei, Mark Ghinovker
  • Patent number: 11870274
    Abstract: A wireless charging device is disclosed, which includes: a charging pad and a first controller. The charging pad includes a plurality of charging units, the plurality of charging units include a first charging unit and a second charging unit. When a first electromagnetic coupling strength between the first charging unit and the to-be-charged device is greater than or equal to a first threshold, the first controller is configured to control the first charging unit to separately charge the to-be-charged device. When both the second electromagnetic coupling strength between the second charging unit and the to-be-charged device and the first electromagnetic coupling strength are less than a first threshold, and are greater than or equal to a second threshold, the first controller is configured to control the first charging unit and the second charging unit to jointly charge the target to-be-charged device.
    Type: Grant
    Filed: January 28, 2021
    Date of Patent: January 9, 2024
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Yongfa Zhu, Tao Ding, Heqian Yang, Changsheng Pei, Zhi Zhang
  • Patent number: 11858366
    Abstract: A vehicle includes: a battery pack including a secondary battery, a battery sensor that detects a state of the secondary battery, and a first control device; a second control device provided separately from the battery pack; and a converter. The first control device is configured to use a detection value of the battery sensor to obtain a current upper limit value indicating an upper limit value of an input current of the secondary battery. The second control device is configured to use a power upper limit value indicating an upper limit value of an input power of the secondary battery to control the input power of the secondary battery. The converter is configured to perform a conversion of the current upper limit value into the power upper limit value.
    Type: Grant
    Filed: December 2, 2020
    Date of Patent: January 2, 2024
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Yoshiaki Kikuchi, Junichi Matsumoto, Akio Uotani
  • Patent number: 11860548
    Abstract: A method of determining a characteristic of one or more processes for manufacturing features on a substrate, the method including: obtaining image data of a plurality of features on a least part of at least one region on a substrate; using the image data to obtain measured data of one or more dimensions of each of at least some of the plurality of features; determining a statistical parameter that is dependent on the variation of the measured data of one or more dimensions of each of at least some of the plurality of features; determining a probability of defective manufacture of features in dependence on a determined number of defective features in the image data; and determining the characteristic of the one or more processes to have the probability of defective manufacture of features and the statistical parameter.
    Type: Grant
    Filed: February 6, 2020
    Date of Patent: January 2, 2024
    Assignee: ASML NETHERLANDS B.V.
    Inventors: Wim Tjibbo Tel, Hermanus Adrianus Dillen, Marc Jurian Kea, Mark John Maslow, Koen Thuijs, Peter David Engblom, Ralph Timotheus Huijgen, Daan Maurits Slotboom, Johannes Catharinus Hubertus Mulkens
  • Patent number: 11850958
    Abstract: A connector unit for a plug-in electrical vehicle includes a first set of terminals for connection with a high-voltage energy storage, a second set of terminals for connection with an electrical propulsion motor, a connector interface having electrical connectors and being configured for temporarily receiving a corresponding connector interface of a charging connector during charging of the high-voltage energy storage of the plug-in electrical vehicle, and a permanent or temporary electrical connection between the first set of terminals and the second set of terminals.
    Type: Grant
    Filed: January 15, 2021
    Date of Patent: December 26, 2023
    Assignee: NINGBO GEELY AUTOMOBILE RESEARCH & DEVELOPMENT CO
    Inventor: Sri Vishnu Gorantla Narayana Murthy
  • Patent number: 11853660
    Abstract: A system for modeling a semiconductor fabrication process includes at least one first processor and at least one second processor. The at least one first processor is configured to provide at least one machine learning (ML) model, which is trained by using a plurality of pairs of images of a design pattern sample and a physical pattern sample. The physical pattern sample is formed from the design pattern sample by using the semiconductor fabrication process. The at least one second processor is configured to provide an input image representing a shape of a design pattern and/or a physical pattern to the at least one first processor and to generate output data defining the physical pattern and/or the design pattern based on an output image received from the at least one first processor.
    Type: Grant
    Filed: April 15, 2021
    Date of Patent: December 26, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyunjoong Kim, Jaepil Shin, Moonhyun Cha, Changwook Jeong
  • Patent number: 11853848
    Abstract: Systems and techniques that facilitate backend quantum runtimes are provided. In various embodiments, a system can comprise a backend receiver component that can access a computer program provided by a client device, wherein the computer program is configured to indicate a quantum computation. In various aspects, the system can further comprise a backend runtime manager component that can host the computer program by instantiating a backend classical computing resource. In various instances, the backend classical computing resource can orchestrate both classical execution of the computer program and quantum execution of the quantum computation indicated by the computer program.
    Type: Grant
    Filed: May 7, 2021
    Date of Patent: December 26, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Blake Johnson, Ismael Faro Sertage, Lev Samuel Bishop, Jay Michael Gambetta, Renier Morales
  • Patent number: 11846889
    Abstract: A diffraction pattern guided source mask optimization (SMO) method that includes determining a source variable region from a diffraction pattern. The source variable region corresponds to one or more areas of a diffraction pattern in a pupil for which one or more pupil variables are to be adjusted. The source variable region in the diffraction pattern includes a plurality of pixels in an image of a selected region of interest in the diffraction pattern. Determining the source variable region can include binarization of the plurality of pixels in the image such that individual pixels are either included in the source variable region or excluded from the source variable region. The method can include adjusting the one or more pupil variables for the one or more areas of the pupil that correspond to the source variable region; and rendering a final pupil based on the adjusted one or more pupil variables.
    Type: Grant
    Filed: February 20, 2020
    Date of Patent: December 19, 2023
    Assignee: ASML NETHERLANDS B.V.
    Inventors: Duan-Fu Stephen Hsu, Dezheng Sun
  • Patent number: 11847535
    Abstract: A quantum computing system includes a first silicon nitride resonator couplable to a first alkali atom, a second silicon resonator couplable to a second alkali atom, and a plurality of lasers for trapping, cooling, and manipulating the first alkali atom and the second alkali atom. Detectors detect a presence of the trapped first alkali atom and the trapped second alkali atom, and a processor is configured to receive at least one input signal from at least one of the detectors, the input signal indicating a presence of the trapped first alkali atom and the trapped second alkali atom, and, based on the received input, control at least some of the plurality of lasers to manipulate at least one of the trapped first alkali atom and the trapped second alkali atom to thereby generate photonic qubits using the trapped first alkali atom or generate entanglement between photonic qubits transmitted to the trapped second alkali atom.
    Type: Grant
    Filed: April 14, 2023
    Date of Patent: December 19, 2023
    Assignees: Yeda Research and Development Co. Ltd., Quantum Source Labs Ltd.
    Inventors: Gil Semo, Ziv Aqua, Oded Melamed, Dan Charash, Serge Rosenblum, Barak Dayan
  • Patent number: 11837308
    Abstract: A method of identifying cell-internal defects: obtaining a circuit design of an integrated circuit, the circuit design including netlists of one or more cells coupled to one another; identifying the netlist corresponding to one of the one or more cells; injecting a defect to one of a plurality of circuit elements and one or more interconnects of the cell; retrieving a first current waveform at a location of the cell where the defect is injected by applying excitations to inputs of the cell; retrieving, without the defect injected, a second current waveform at the location of the cell by applying the same excitations to the inputs of the cell; and selectively annotating, based on the first current waveform and the second current waveform, an input/output table of the cell with the defect.
    Type: Grant
    Filed: April 5, 2022
    Date of Patent: December 5, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ankita Patidar, Sandeep Kumar Goel
  • Patent number: 11823037
    Abstract: A neuromorphic analog signal processor includes a flexible circuit corresponding to an analog neural network. The flexible circuit includes operational amplifiers, each operational amplifier corresponding to an analog neuron. The flexible circuit also includes photoresistors or photodiodes interconnecting the operational amplifiers, and illumination sources. Each illumination source transmits light to a corresponding photoresistor or photodiode, thereby changing the resistance as a function of brightness of applied light. The flexible circuit also includes control circuits, each control circuit configured to apply a pulse-width modulation corresponding to a weight value, thereby causing pulsed signals at the illumination sources. The flexible circuit also includes a memory circuit coupled to the circuits.
    Type: Grant
    Filed: February 28, 2023
    Date of Patent: November 21, 2023
    Assignee: PolyN Technology Limited
    Inventors: Boris Maslov, Aleksandrs Timofejevs
  • Patent number: 11815808
    Abstract: A method for source mask optimization with a lithographic projection apparatus. The method includes determining a multi-variable source mask optimization function using a plurality of tunable design variables for an illumination system of the lithographic projection apparatus, a projection optics of the lithographic projection apparatus to image a mask design layout onto a substrate, and the mask design layout. The multi-variable source mask optimization function may account for imaging variation across different positions in an exposure slit corresponding to different stripes of the mask design layout exposed by a same slit position of the exposure apparatus. The method includes iteratively adjusting the plurality of tunable design variables in the multi-variable source mask optimization function until a termination condition is satisfied.
    Type: Grant
    Filed: October 3, 2019
    Date of Patent: November 14, 2023
    Assignee: ASML NETHERLANDS B.V.
    Inventors: Kars Zeger Troost, Eelco Van Setten, Duan-Fu Stephen Hsu
  • Patent number: 11809821
    Abstract: A computer-implemented method characterizes and controls performance of a set of device nodes in a distributed heterogeneous computing and control system. The device nodes are in physically distinct locations, in communication with one another over a network. One or more of the device nodes require different application programming code due to differences in hardware configuration or software configuration. The method includes configuring, by a design computer, for introduction into each distinct one of the device nodes, a corresponding communication facility and a corresponding dashboard instance. After introduction of the communication facility and dashboard instance into each device node, the design computer includes a communication facility in communication with the corresponding communication facility of each device node.
    Type: Grant
    Filed: May 11, 2021
    Date of Patent: November 7, 2023
    Assignee: Prescient Devices, Inc.
    Inventor: Andrew Wang
  • Patent number: 11800646
    Abstract: Methods and systems are provided for designing an optimized stack up of layers of a PCB (Printed Circuit Board). A set of constraints is determined for the PCB stack up, where the constraints limit a total number of layers, a number of signal layers, and a thickness of the PCB stack up. Each of the constraints on the PCB stack up is encoded as an equality or an inequality. The set of equalities and inequalities is solved using integer programming techniques to identify an optimal solution to the set of constraints on the PCB stack up, where the optimal solution specifies an arrangement of signaling layers for the PCB. An estimate is generated for impedances and losses for the optimal PCB stack up. The constraints on a PCB stack up are modified when the estimated impedances and losses for the optimal PCB stack up are above a target threshold.
    Type: Grant
    Filed: July 22, 2022
    Date of Patent: October 24, 2023
    Assignee: Dell Products, L.P.
    Inventors: Bhavesh Govindbhai Patel, Arun Chada, Bhyrav M. Mutnury
  • Patent number: 11798737
    Abstract: A charging pad for charging one or more receiver devices is disclosed. The charging pad includes a power drive unit configured to generate a first AC voltage signal having a first frequency and a second AC voltage signal having a second frequency. Further, the charging pad includes a transmitting unit including a single power exchange coil coupled to the power drive unit, wherein the single power exchange coil includes a first coil segment configured to transmit the first AC voltage signal having the first frequency when the first AC voltage signal is received from the power drive unit. Also, the single power exchange coil includes a second coil segment configured to transmit the second AC voltage signal having the second frequency when the second AC voltage signal is received from the power drive unit.
    Type: Grant
    Filed: December 3, 2021
    Date of Patent: October 24, 2023
    Assignee: General Electric Company
    Inventors: Suma Memana Narayana Bhat, Deepak Aravind, Somakumar Ramachandrapanicker, Arun Kumar Raghunathan
  • Patent number: 11797744
    Abstract: A specification for a semi-conductor chip is received. The specification specifies a set of photomasks associated with a metal layer of the semi-conductor chip. Multiple portions of an area of the metal layer are identified. A respective image is generated for each portion of the area based on the photomasks. A respective drawn density of metal wires for each portion of the area is calculated. A trained machine learning model is invoked to predict a respective silicon density of metal wires for each respective portion of the area based on an image and a drawn density for the respective portion of the area. A silicon density for the area of the metal layer is calculated based on a combination of predicted silicon densities for the multiple portions of the area. The combination is based on an average value of the predicted silicon densities for the multiple portions of the area.
    Type: Grant
    Filed: February 18, 2021
    Date of Patent: October 24, 2023
    Assignee: ANSYS Inc.
    Inventors: Wen-Tze Chuang, Norman Chang, Lei Yin, Bolong Zhang, Xi Chen, Jay Prakash Pathak, En Cih Yang, Jimin Wen, Akhilesh Kumar, Ming-Chih Shih, Ying Shiun Li
  • Patent number: 11790261
    Abstract: Technology is disclosed herein that the enhances the measurability and scalability of qubits in a quantum computing environment. In an implementation, a superconducting amplifier device comprises a parametric amplifier and a tunable coupling between the parametric amplifier and a readout cavity external to the superconducting amplifier device. The tunable coupling allows an entangled signal, associated with a qubit in the readout cavity, to transfer from the readout cavity to the parametric amplifier. The parametric amplifier amplifies the entangled signal to produce an amplified signal as output to a measurement sub-system.
    Type: Grant
    Filed: March 4, 2021
    Date of Patent: October 17, 2023
    Assignees: The Regents of the University of Colorado, a body corporate, Universitat Innsbruck
    Inventors: Eric Rosenthal, Konrad Lehnert, Christian Schneider
  • Patent number: 11784098
    Abstract: A method of determining overlay of a patterning process, the method including: obtaining a detected representation of radiation redirected by one or more physical instances of a unit cell, wherein the unit cell has geometric symmetry at a nominal value of overlay and wherein the detected representation of the radiation was obtained by illuminating a substrate with a radiation beam such that a beam spot on the substrate was filled with the one or more physical instances of the unit cell; and determining, from optical characteristic values from the detected radiation representation, a value of a first overlay for the unit cell separately from a second overlay for the unit cell that is also obtainable from the same optical characteristic values, wherein the first overlay is in a different direction than the second overlay or between a different combination of parts of the unit cell than the second overlay.
    Type: Grant
    Filed: August 20, 2021
    Date of Patent: October 10, 2023
    Assignee: ASML NETHERLANDS B.V.
    Inventors: Adriaan Johan Van Leest, Anagnostis Tsiatmas, Paul Christiaan Hinnen, Elliott Gerard McNamara, Alok Verma, Thomas Theeuwes, Hugo Augustinus Joseph Cramer
  • Patent number: 11775711
    Abstract: For manufacturing-related reasons, the qubits of known quantum computers are not to be regarded as equivalent, but instead a standard quantum computer has not only high-performance qubits with long decoherence times and good fidelities of operation but also low-performance qubits with short decoherence times and poor fidelities of operation. The invention utilizes these by subdividing a system to be modeled with such a quantum computer into a bath part of low relevance and a cluster part of high relevance, wherein a rough description of the bath part is assigned to the low-performance qubits and an exact description of the cluster part is assigned to the high-performance qubits.
    Type: Grant
    Filed: February 6, 2020
    Date of Patent: October 3, 2023
    Assignee: HQS Quantum Simulations GmbH
    Inventors: Michael Marthaler, Jan-Michael Reiner, Sebastian Zanker, Iris Schwenk
  • Patent number: 11775731
    Abstract: A stencil-avoidance design method, a stencil-avoidance design device, an electronic device, and a non-transitory storage medium are provided. The method includes: obtaining a plurality of first regions and a plurality of first stencil aperture regions; determining whether a shortest distance between a selected first region of the plurality of first regions and a selected first stencil aperture region of the plurality of first stencil aperture regions is within a preset threshold range; further obtaining a second region and a second stencil aperture region if the shortest distance is within the preset threshold range, and then obtaining a third region; performing a collision step if a collision test is required, and obtaining a final stencil aperture region. The above method can improve the efficiency, accuracy, coverage, and comprehensiveness of the stencil avoidance design.
    Type: Grant
    Filed: May 31, 2021
    Date of Patent: October 3, 2023
    Assignee: VAYO (SHANGHAI) TECHNOLOGY CO., LTD.
    Inventors: Pan Su, Dujuan Li, Shengjie Qian, Jishuo Liu