Abstract: A field effect transistor (FET) for an nFET and/or a pFET device including a substrate and a fin including at least one channel region decoupled from the substrate. The FET also includes a source electrode and a drain electrode on opposite sides of the fin, and a gate stack extending along a pair of sidewalls of the channel region of the fin. The gate stack includes a gate dielectric layer and a metal layer on the gate dielectric layer. The FET also includes an oxide separation region separating the channel region of the fin from the substrate. The oxide separation region includes a dielectric material that includes a portion of the gate dielectric layer of the gate stack. The oxide separation region extends completely from a surface of the channel region facing the substrate to a surface of the substrate facing the channel region.

Abstract: A quantum dot, and a light emitting device including the same is provided. The quantum dot includes a semiconductor nanocrystal and an organic ligand bound to the surface of the semiconductor nanocrystal, wherein the organic ligand includes a first ligand derived from a first thiol compound including a C12 or more aliphatic hydrocarbon group, and a second ligand derived from a second thiol compound including a C8 or less aliphatic hydrocarbon group.

Abstract: A semiconductor package structure includes a first semiconductor die, an encapsulant surrounding the first semiconductor die, and a redistribution layer (RDL) electrically coupled to the first semiconductor die. The encapsulant has a first surface over the first semiconductor die and a second surface under the first semiconductor die. The RDL has a first portion under the first surface of the encapsulant and a second portion over the first surface of the encapsulant.

Abstract: Methods produce integrated circuit structures that include (among other components) fins extending from a first layer, source/drain structures on the fins, source/drain contacts on the source/drain structures, an insulator on the source/drain contacts defining trenches between the source/drain contacts, gate conductors in a lower portion of the trenches adjacent the fins, a first liner material lining a middle portion and an upper portion of the trenches, a fill material in the middle portion of the trenches, and a second material in the upper portion of the trenches. The first liner material is on the gate conductors in the trenches.

Abstract: A data storage system is described that uses wafer-level packaging. In one embodiment an apparatus includes a silicon wafer, a plurality of memory cells formed directly on the wafer, an encapsulant formed over the memory cells, a plurality of wiring connections to connect the memory cells to an external interface, a memory controller, and an external interface.

Abstract: A semiconductor device manufacturing technique which allows reduction of semiconductor chip size. First, a pad and other wires are formed over an insulating film. A surface protective film is formed over the insulating film including the pad and wires, and an opening is made in the surface protective film. The opening lies over the pad and exposes a surface of the pad. A bump electrode is formed over the surface protective film including the opening. Here, the pad is smaller than the bump electrode. Consequently, the wires are arranged just beneath the bump electrode in the same layer as the pad 10. In other words, the wires are arranged in space which becomes available because the pad is small enough.

Abstract: A display device includes a substrate including an outer area neighboring a border; and an insulating layer positioned over the substrate and including a plurality of openings positioned over the outer area. The openings are arranged to be spaced from each other in a direction. The display device further includes a wavy line extending in the direction and passing the plurality of openings.

Abstract: A power converter circuit includes an inductor and rectifier circuit having an inductor connected in series with an electronic switch, and a rectifier circuit, and a controller for generating a drive signal for driving the electronic switch. The electronic switch has drain, source and gate nodes, drift and compensation cells each including a drift region of a first doping type and a compensation region of a second doping type, and a control structure connected between the drift region of each of the drift and compensation cells and the source node. Each drift region is coupled to the drain node and each compensation region cells is coupled to the source node. A first type doping concentration N1 of the drift region is higher than a first doping level L1, and a second type doping concentration N2 of the compensation region is higher than a second doping level L2.

Abstract: In one example, a method includes performing a first etching process to pattern a dielectric layer and expose a contact etch stop layer, performing a second etching process to remove the etch stop layer and expose a top surface of an underlying feature, performing a third etching process to laterally recess the etch stop layer, and depositing a conductive material over the underlying feature to create a conductive feature in direct contact with the underlying feature.

Abstract: A method for aligning and contacting a first substrate with a second substrate using a plurality of detection units and a corresponding device for alignment and contact.

Abstract: The present disclosure provides a display panel and a fabrication method thereof and a display device. The display panel includes a first substrate and a second substrate, which are aligned and assembled to form a cell, and a sealant sandwiched between the first substrate and the second substrate, wherein a hollow structure is arranged in at least one of a first surface layer of the first substrate facing the second substrate and a second surface layer of the second substrate facing the first substrate, and wherein a portion of the sealant is embedded in the hollow structure.

Abstract: An active matrix substrate (100) according to an embodiment of the present invention has a display region (DR) defined by a plurality of pixel regions (P) arranged in a matrix pattern, and a peripheral region (FR) located around the display region. The active matrix substrate includes a substrate (1), a first TFT (10) supported on the substrate and including a crystalline silicon semiconductor layer (11), and a second TFT (20) supported on the substrate and including an oxide semiconductor layer (21). The first TFT and the second TFT each have a top gate structure. The oxide semiconductor layer is located below the crystalline silicon semiconductor layer.

Abstract: At least one method, apparatus and system disclosed herein involves forming local interconnect regions during semiconductor device manufacturing. A plurality of fins are formed on a semiconductor substrate. A gate region is over a portion of the fins. A trench silicide (TS) region is formed adjacent a portion of the gate region. The TS region comprises a first TS metal feature and a second TS metal feature. A bi-layer self-aligned contact (SAC) cap is formed over a first portion of the TS region and electrically coupled to a portion of the gate region. A portion of the bi-layer SAC cap is removed to form a first void. A first local interconnect feature is formed in the first void.

Abstract: According to one embodiment, a semiconductor device includes a semiconductor member, drain electrodes, a drain interconnect portion, and a drain conductive portion. The semiconductor member includes first and second semiconductor regions. The drain electrodes extend along a first direction, are arranged in a second direction crossing the first direction, and are provided at the first semiconductor region. A direction from the first semiconductor region toward the second semiconductor region is aligned with the first direction. The drain interconnect portion extends along the second direction and is electrically connected to the drain electrodes. The drain conductive portion is electrically connected to the drain interconnect portion. The drain conductive portion includes first and second conductive regions. A portion of the drain interconnect portion is between the first conductive region and the first semiconductor region in a third direction.

Abstract: A semiconductor device includes a substrate, at least one trench, an insulating layer, a lower metal layer, a negative capacitance material layer, and an upper metal layer. The trench has an inner surface in the substrate. The insulating layer is disposed on and lining the inner surface of the trench. The lower metal layer is disposed on the insulating layer and partially filling the trench. The negative capacitance material layer is disposed on and lining the insulating layer and the lower metal layer, in which a remained portion of the trench is defined by the negative capacitance material layer. The upper metal layer is disposed on the negative capacitance material layer and filling the remained portion of the trench.

Abstract: A chip on film package is disclosed, including a flexible film, a patterned circuit layer, a chip, and a dummy metal layer. The flexible film includes a first surface and a second surface opposite to the first surface. The patterned circuit layer is disposed on the first surface. The chip is mounted on the first surface and electrically connected to the patterned circuit layer. The dummy metal layer covers the second surface capable of dissipating heat of the chip. The dummy metal layer is electrically insulated from the patterned circuit layer.

Abstract: A magnetic memory device may include magnetic tunnel junction patterns on a substrate, a conductive line extending between the substrate and the magnetic tunnel junction patterns and in contact with bottom surfaces of the magnetic tunnel junction patterns, and a bottom pattern located between the conductive line and the substrate and in contact with a bottom surface of the conductive line. The material of the conductive line may have a first lattice constant, and the material of the bottom pattern may have a second lattice constant that is less than the first lattice constant of the conductive line. Alternatively or additionally, the bottom pattern includes a metal nitride, and a nitrogen content of the bottom pattern is higher than a metal element content of the metal element.

Abstract: This disclosure relates to a display and a method of fabricating the display. According to some embodiments, the display may comprise: an encapsulation sidewall; at least one isolation column adjacent to the encapsulation sidewall; and a processing module coupled with the at least one isolation column, configured to apply a voltage signal to the at least one isolation column according to a height of the encapsulation sidewall, such that the at least one isolation column deforms.

Abstract: A super-junction structure is formed by alternately arrayed pluralities of N-pillars and of P-pillars. The P-pillars are formed by P-type materials filled in super-junction trenches. The super-junction trenches are formed in an N-type epitaxial layer, each formed by a bottom trench and a top trench stacked together. A side angle of the bottom trenches is greater than 90°, and the width of the bottom surface of each bottom trench is greater than that of the top surface of the trench. The side angle of the top trenches is smaller than 90°, and the width of the bottom surface of each top trench is smaller than the top surface of the trench. The super-junction trenches are of a waisted structure. The bottom trenches increase the bottom width of the super-junction trenches and improve the depletion of the bottoms of the N-pillars, increasing the breakdown voltage of the super-junction structure.

Abstract: A capacitor includes a first electrode; a second electrode facing the first electrode; and a dielectric layer which is disposed between the first electrode and the second electrode and which is in contact with the first electrode. The first electrode includes a first portion including an interface between the first electrode and the dielectric layer, the dielectric layer includes a second portion including the interface, and the first portion and the second portion each contain silicon. A concentration distribution of the silicon along a thickness direction of the first portion and the second portion includes a convex portion intersecting the interface.