Abstract: The present disclosure, in some embodiments, relates to a resistive random access memory (RRAM) device. The RRAM device includes a first electrode over a substrate and a second electrode over the substrate. A data storage structure is disposed between the first electrode and the second electrode. The data storage structure has a plurality of sub-layers including one or more metals having non-zero concentrations that change as a distance from the first electrode increases.

Abstract: An integrated circuit including: a power rail including first and second conductive lines spaced apart from each other in a vertical direction, wherein the first and second conductive lines extend in parallel to each other in a first horizontal direction, and are electrically connected to each other, to supply power to a first standard cell, wherein the first and second conductive lines are disposed at a boundary of the first standard cell; and a third conductive line between the first and second conductive lines and extending in a second horizontal direction orthogonal to the first horizontal direction, to transfer an input signal or an output signal of the first standard cell.

Abstract: A light-emitting device includes a semiconductor stack including a first semiconductor layer, a second semiconductor layer, and an active layer emitting an UV light, formed between the first semiconductor layer and the second semiconductor layer; a first transparent conductive layer formed on the second semiconductor layer, the first transparent conductive layer including metal oxide; and a second transparent conductive layer formed on the first transparent conductive layer, the second transparent conductive layer including graphene, wherein the first transparent conductive layer is continuously formed over a top surface of the second semiconductor layer, the first transparent conductive layer comprises a thickness smaller than 10 nm.

Abstract: A light emitting diode array is provide to include: a substrate; light emitting diodes positioned over the substrate, each including a first semiconductor layer, an active layer, and a second semiconductor layer, wherein each light emitting diode is disposed to form a first via hole structure exposing a portion of the corresponding first semiconductor layer; lower electrodes disposed over the second semiconductor layer; a first interlayer insulating layer disposed over the lower electrodes and configured to expose the portion of the first semiconductor layer of corresponding light emitting diodes; upper electrodes electrically connected to the first semiconductor layer through the first via hole structure, wherein the first via hole structure is disposed in parallel with one side of the corresponding second semiconductor layer and the first interlayer insulating layer is disposed to form a second via hole structure exposing a portion of the lower electrodes.

Abstract: Integrated circuit devices are provided. An integrated circuit device includes a substrate and a device isolation film on the substrate. An active region of the substrate is defined by the device isolation film on the substrate and has a first width in a horizontal direction. A gate electrode is on the active region and has a second width equal to or less than the first width of the active region in the horizontal direction. The integrated circuit device includes an insulating spacer over the device isolation film and the active region.

Abstract: There is provided a technique that includes (a) forming a film containing silicon, carbon and nitrogen having a carbon concentration within a range from 10 at % to 15 at % on a substrate; (b) performing an oxidation process with respect to the substrate where the film is exposed on a surface thereof; and (c) performing a process using hydrogen fluoride with respect to the substrate where the film is exposed on the surface thereof after the oxidation process is performed.

Abstract: Methods and systems for line cut by multi-color patterning techniques are presented. In an embodiment, a method may include providing a substrate. The method may also include forming a first feature on the substrate, the first feature having a cap formed of a first material. Additionally, the method may include forming a second feature on the substrate, the second feature having a cap formed of a second material. In still a further embodiment, the method may include selectively removing the second feature using an etch process that etches the first material at a first etch rate and etches the second material at a second etch rate, wherein the second etch rate is higher than the first etch rate.

Abstract: A display device includes a display panel and an anti-reflection unit directly disposed on the display panel. The display panel includes first to third light emitting elements, each of which includes first and second electrodes, and a light emitting layer, which is disposed between the first electrode and the second electrode. The pixel definition layer includes a first portion, in which a light-emitting opening exposing the first electrode is defined, and a second portion, which is disposed on and overlapped with the first portion. The anti-reflection unit includes first to third color filters overlapped with the first to third light emitting elements, respectively, and a color spacer, which is overlapped with the second portion and is thicker than each of the first to third color filters.

Abstract: Thermally-sensitive structures and methods for sensing the temperature in a region of a FET during device operation are described. The region may be at or near a region of highest temperature achieved in the FET. Metal resistance thermometry (MRT) can be implemented with gate or source structures to evaluate the temperature of the FET.

Abstract: The present disclosure relates to a method for manufacturing an OLED device, an OLED device and a display panel. The method for manufacturing the OLED device comprises: forming a first electrode layer on a substrate; forming at least one layer of inorganic film at a position on the first electrode layer corresponding to a pixel defining layer; breaking a first organic layer at an etching angle of the at least one layer of inorganic film when forming the first organic layer; forming the pixel defining layer on the inorganic film; forming the first organic layer on the first electrode layer, the inorganic film and the pixel defining layer; and forming a light emitting layer, a second organic layer and a second electrode layer in this order on the first organic layer.

Abstract: A semiconductor memory device includes a circuit chip including a first substrate, peripheral circuit elements which are defined on the first substrate and a first dielectric layer which covers the peripheral circuit elements, and having first pads which are coupled to the peripheral circuit elements, on one surface thereof; a memory chip including a second substrate which is disposed on a base dielectric layer, a memory cell array which is defined on the second substrate and a second dielectric layer which covers the memory cell array, and having second pads which are coupled with the first pads, on one surface thereof which is bonded with the one surface of the circuit chip; a contact passing through the base dielectric layer and the second dielectric layer; and one or more dummy contacts passing through the base dielectric layer and the second dielectric layer, and disposed around the contact.

Abstract: High density integrated circuit (IC) capacitor structures and fabrication methods that increase the capacitive density of integrated capacitors with little or no reduction in Q-factor by using a stacked high-density integrated capacitor structure that includes substrate-contact (“S-contact”) capacitor plates. Embodiments include a plurality of S-contact plates fabricated in electrical connection with a capacitor formed in a metal interconnect layer. Some embodiments include interstitial S-contact plates to provide additional capacitive density. Embodiments may also utilize single-layer transfer (SLT) and double-layer transfer (DLT) techniques to create ICs with high density, high Q-factor capacitors. Such capacitors can be beneficially combined with other structures made possible in SLT and DLT IC structures, such as metal interconnect layer capacitors and inductors, and one or more FETs having a conductive aligned supplemental gate.

Abstract: A printable component structure includes a chiplet having a semiconductor structure with a top side and a bottom side, one or more top electrical contacts on the top side of the semiconductor structure, and one or more bottom electrical contacts on the bottom side of the semiconductor structure. One or more electrically conductive spikes are in electrical contact with the one or more top electrical contacts. Each spike protrudes from the top side of the semiconductor structure or a layer in contact with the top side of the semiconductor structure.

Abstract: Pursuant to some embodiments of the present invention, transistor devices are provided that include a semiconductor structure, a gate finger extending on the semiconductor structure in a first direction, and a gate interconnect extending in the first direction and configured to be coupled to a gate signal at an interior position of the gate interconnect, where the gate interconnect is connected to the gate finger at a position offset from the interior position of the gate interconnect.

Abstract: Techniques for tight pitch patterning of fins using a cyclic selective deposition process are provided. In one aspect, a method of patterning fins in a wafer includes: forming at least one mandrel on the wafer; forming alternating layers of a first dielectric and a second dielectric alongside the at least one mandrel; removing the at least one mandrel; removing either the first dielectric or the second dielectric; and patterning the fins in the wafer using whichever of the first dielectric or the second dielectric that remains as fin hardmasks. A finFET device and method for forming a finFET device are also provided.

Abstract: In a semiconductor device, an insulating film is disposed between an upper surface of a substrate and a floating gate of a flash memory, a first oxide film is disposed directly above the floating gate, a silicon nitride film is disposed on an upper surface of the first oxide film, and a second oxide film made of silicon oxide film is disposed on an upper surface of the silicon nitride film.

Abstract: A transistor device includes a semiconductor structure, a plurality of gate fingers extending on the semiconductor structure in a first direction, a plurality of gate interconnects that each have a first end and a second end extending on the semiconductor structure in the first direction, wherein each gate interconnect is connected to a respective gate finger by a plurality of first conductive vias, and a plurality of gate runners extending on the semiconductor structure in the first direction. At least one gate interconnect of the gate interconnects is connected to one of the gate runners by a second conductive via at an interior position of the at least one gate interconnect that is remote from the first end and the second end of the at least one gate interconnect.

Abstract: A method for depositing a silicon nitride film is provided. In the method, an adsorption blocking region is formed such that a chlorine-containing gas conformally adsorbs on a surface of a substrate by adsorbing chlorine radicals on the surface of the substrate. A source gas that contains silicon and chlorine is adsorbed on the adsorption blocking region adsorbed on the surface of the substrate. A silicon nitride film is deposited on the surface of the substrate by supplying a nitriding gas activated by plasma to the source gas adsorbed on the surface of the substrate.

Abstract: A light emitting device includes a first electrode, a hole transporting layer in contact with the first electrode, a second electrode, an electron transporting layer in contact with the second electrode; and an emissive layer between the hole transporting layer and the electron transporting layer. The emissive layer includes a metal-assisted delayed fluorescent (MADF) emitter, a fluorescent emitter, and a host, and the MADF emitter harvests electrogenerated excitons and transfers energy to the fluorescent emitter.

Abstract: A semiconductor device includes a substrate provided with an electronic device, an interlayer dielectric (ILD) layer formed over the electronic device, a wiring pattern formed on the ILD layer and a contact formed in the ILD layer and physically and electrically connecting the wiring pattern to a conductive region of the electronic device. An insulating liner layer is provided on sidewalls of the contact between the contact and the ILD layer. A height of the insulating liner layer measured from a top of the conductive region of the electronic device is less than 90% of a height of the contact measured between the top of the conductive region and a level of an interface between the ILD layer and the wiring pattern.