Abstract: A semiconductor device includes a semiconductor substrate having a first conductivity type, a first well region formed in a portion of the semiconductor substrate, having a second conductivity type that is the opposite of the first conductivity type. A second well region is formed in a portion of the first well region, having the first conductivity type. A first gate structure is formed over a portion of the second well region and a portion of the first well region. A first doped region is formed in a portion of the second well region. A second doped region is formed in a portion of the first well region, having the second conductivity type. A second dielectric layer is formed over a portion of the first gate structure, a portion of the first well region, and a portion of the second doped region.

Abstract: A method of forming a semiconductor device package includes: (1) providing an electronic device including an active surface and a contact pad adjacent to the active surface; (2) forming a package body encapsulating portions of the electronic device; and (3) forming a redistribution stack, including: forming a dielectric layer over a front surface of the package body, the dielectric layer defining a first opening exposing at least a portion of the contact pad; and forming a redistribution layer (RDL) over the dielectric layer, the RDL including a first trace, wherein the first trace includes a first portion extending over the dielectric layer along a first longitudinal direction adjacent to the first opening, and a second portion disposed in the first opening and extending between the first portion of the first trace and the exposed portion of the contact pad, wherein the second portion of the first trace has a maximum width along a first transverse direction orthogonal to the first longitudinal direction, and

Abstract: A Magnetic Tunnel Junction (MTJ) can include an annular structure and a planar reference magnetic layer disposed about the annular structure. The annular structure can include an annular non-magnetic layer disposed about an annular conductive layer, an annular free magnetic layer disposed about the annular non-magnetic layer, and an annular tunnel insulator disposed about the annular free magnetic layer. The planar reference magnetic layer can be separated from the free magnetic layer by the annular tunnel barrier layer.

Abstract: A method of forming an array of capacitors and access transistors there-above comprises forming access transistor trenches partially into insulative material. The trenches individually comprise longitudinally-spaced masked portions and longitudinally-spaced openings in the trenches longitudinally between the masked portions. The trench openings have walls therein extending longitudinally in and along the individual trench openings against laterally-opposing sides of the trenches. At least some of the insulative material that is under the trench openings is removed through bases of the trench openings between the walls and the masked portions to form individual capacitor openings in the insulative material that is lower than the walls. Individual capacitors are formed in the individual capacitor openings. A line of access transistors is formed in the individual trenches. The line of access transistors electrically couples to the individual capacitors that are along that line.

Abstract: An electro-optical device includes a circuit substrate including a flattening layer provided on a surface of the circuit substrate, at least one electro-optical element provided on the flattening layer, a sealing film configured to seal the electro-optical element and including at least a resin layer, and a frame-shaped bank surrounding the flattening layer and covered by the resin layer on an inner side of the frame-shaped bank. In a plan view, an unevenness is provided at a peripheral edge of the flattening layer facing the frame-shaped bank.

Abstract: A semiconductor device package includes: (1) an electronic device including an active surface and a contact pad adjacent to the active surface; and (2) a redistribution stack including a dielectric layer disposed over the active surface and defining a first opening exposing at least a portion of the contact pad; and a redistribution layer (RDL) disposed over the dielectric layer and including a first trace, wherein the first trace includes a first portion extending over the dielectric layer along a first longitudinal direction adjacent to the first opening, and a second portion disposed in the first opening and extending between the first portion of the first trace and the exposed portion of the contact pad, wherein the second portion of the first trace has a maximum width along a first transverse direction orthogonal to the first longitudinal direction, and the maximum width of the second portion of the first trace is no greater than 3 times of a width of the first portion of the first trace, wherein the sec

Abstract: A tunnel field-effect transistor (TFET), comprising a first source/drain layer comprising a first polar sidewall; a second source/drain layer surrounding the first source/drain layer, wherein the second source/drain layer and the first source/drain layer are of opposite conductivity types; and a semiconductor interlayer between the second source/drain layer and first polar sidewall of the first source/drain layer.

Abstract: A method for forming a semiconductor device is provided. A plurality of trenches are formed in the substrate. An isolation oxide layer is formed in the trenches and on the substrate. A shield polysilicon is deposited in the trenches and on the isolation oxide layer on the substrate. A first etching process is performed to remove a first portion of the shield polysilicon. A first removal process is performed to remove a first portion of the isolation oxide layer. A second etching process is performed to remove a second portion of the shield polysilicon. A second removal process is performed to remove a second portion of the isolation oxide layer. An inter-poly oxide layer is formed on the remaining shield polysilicon and the remaining isolation oxide layer, wherein the inter-poly oxide layer has a concave top surface.

Abstract: To make it possible to improve display quality more. Provided is a display device including: a pixel unit in which a plurality of pixel circuits (PIX_A, PIX_B, PIX_C) each of which includes a light emitting element and a driving circuit configured to drive the light emitting element are arranged in a matrix form. In a diffusion layer in which transistors included in the driving circuits of the pixel circuits (PIX_A, PIX_B, PIX_C) are formed, an electricity supply region (223) that is an active area for supplying an electric potential to a well is provided between mutually adjacent ones of the pixel circuits (PIX_A, PIX_B, PIX_C).

Abstract: The present disclosure, in some embodiments, relates to a resistive random access memory (RRAM) device. The RRAM device includes a lower electrode over a conductive interconnect, and an upper electrode over the lower electrode. A data storage structure is disposed between the lower electrode and the upper electrode. The data storage structure includes a plurality of metal oxide layers having one or more metals from a first group of metals. A concentration of the one or more metals from the first group of metals changes as a distance from the lower electrode increases.

Abstract: A method of forming a semiconductor structure is disclosed, comprising providing a substrate, forming at least a gate trench extending along a first direction in the substrate, forming a gate dielectric layer conformally covering the gate trench, forming a sacrificial layer on the gate dielectric layer and completely filling the gate trench, forming a plurality of openings through the sacrificial layer in the gate trench thereby exposing a portion of the gate dielectric layer, forming a dielectric material in the openings, performing an etching back process to remove a portion of the dielectric material until the dielectric material only remains at a lower portion of each of the openings thereby obtaining a plurality of intervening structures, removing the sacrificial layer, and forming a gate metal filling the gate trench, wherein the intervening structures are disposed between the gate metal and the gate dielectric layer.

Abstract: A memory element can include a first electrode; at least one switching layer formed over the first electrode; a second electrode layer; and at least one conductive cap layer formed over the second electrode layer having substantially no grain boundaries extending through to the second electrode layer; wherein the at least one switching layer is programmable between different impedance states by application of electric fields via that first and second electrode. Methods of forming such memory elements are also disclosed.

Abstract: A semiconductor device is provided with a semiconductor element having a plurality of electrodes, a plurality of terminals electrically connected to the plurality of electrodes, and a sealing resin covering the semiconductor element. The sealing resin covers the plurality of terminals such that a bottom surface of the semiconductor element in a thickness direction is exposed. A first terminal, which is one of the plurality of terminals, is disposed in a position that overlaps a first electrode, which is one of the plurality of electrodes, when viewed in the thickness direction. The semiconductor device is provided with a conductive connection member that contacts both the first terminal and the first electrode.

Abstract: A semiconductor device includes a floating buried doped region, a first doped region disposed between the floating buried doped region and a first major surface, and a semiconductor region disposed between the floating buried doped region and a second major surface. A trench isolation structure extends from the first major surface and terminates within the semiconductor region and the floating buried doped region abuts the trench isolation structure. A second doped region is disposed in the first doped region has an opposite conductivity type to the first doped region. A first isolation device is disposed in the first doped region and is configured to divert current injected into the semiconductor device from other regions thereby delaying the triggering of an internal SCR structure. In one embodiment, a second isolation structure is disposed within the first doped region and is configured to disrupt a leakage path along a sidewall surface of the trench isolation structure.

Abstract: According to one embodiment, the source layer includes a semiconductor layer including a dopant. The columnar portions are disposed in an area between the separation portions. The columnar portions extend in the stacking direction through the stacked body and through the semiconductor layer. The columnar portions include a plurality of semiconductor bodies including sidewall portions contacting the semiconductor layer. The dopant diffusion prevention film is provided inside the semiconductor layer and separated from the columnar portions in an area between the columnar portions. The dopant diffusion prevention film is not provided inside the semiconductor layer in an area between the separation portion and the columnar portions.

Abstract: A display device includes a substrate including an outer area neighboring a border; and an insulating layer positioned over the substrate and including a plurality of openings positioned over the outer area. The openings are arranged to be spaced from each other in a direction. The display device further includes a wavy line extending in the direction and passing the plurality of openings.

Abstract: A semiconductor capacitor includes a semiconductor substrate, an electrode group formed on the semiconductor substrate, and a plurality of insulators sandwiched between the electrode groups to form a plurality of capacitors. At least one of the plurality of capacitors is set to be different from at least one of a tolerance, which is a capability of the capacitors to withstand a prescribed voltage, and a conductance, which is an ease with which a leakage current flows in the capacitors.

Abstract: Methods for gapfilling semiconductor device features, such as high aspect ratio trenches, with amorphous silicon (a-Si) film that involves pretreating the surface of the substrate to modify the underlying hydroxy-terminated silicon (Si—OH) or hydrogen-terminated silicon (Si—H) surface to oxynitride-terminated silicon (Si—ON) or nitride-terminated silicon (Si—N) and enhance the subsequent a-Si deposition are provided. First, a substrate having features formed in a first surface of the substrate is provided. The surface of the substrate is then pretreated to enhance the surface of the substrate for the flowable deposition of amorphous silicon that follows. A flowable deposition process is then performed to deposit a flowable silicon layer over the surface of the substrate. Methods described herein generally improve overall etch selectivity by the conformal silicon deposition and the flowable silicon deposition process to realize seam-free gapfilling between features with high quality amorphous silicon film.

Abstract: A transistor device includes a semiconductor structure, a plurality of gate fingers extending on the semiconductor structure in a first direction, a plurality of gate interconnects that each have a first end and a second end extending on the semiconductor structure in the first direction, wherein each gate interconnect is connected to a respective gate finger by a plurality of first conductive vias, and a plurality of gate runners extending on the semiconductor structure in the first direction. At least one gate interconnect of the gate interconnects is connected to one of the gate runners by a second conductive via at an interior position of the at least one gate interconnect that is remote from the first end and the second end of the at least one gate interconnect.

Abstract: Integrated circuits (ICs) employing additional output vertical interconnect access(es) (via(s)) coupled to a circuit output via to decrease circuit output resistance and related methods are disclosed. In exemplary aspects, an output metal interconnect is formed in the IC that extends between a first output contact connected to an output transistor(s) of a circuit, and across an adjacent dummy gate to a second output contact area on the opposite side of the dummy gate from the signal output node. A second output via is connected to the output metal interconnect in the second output contact area. A metal line in a metal layer above the diffusion area and metal contacts is connected to the output via and second output via having parallel output via resistances to reduce the output via resistance of the output transistor(s) of the circuit, and thus reduces the overall resistance of the signal output node of the circuit.