Abstract: An organic interposer includes dielectric material layers embedding redistribution interconnect structures, package-side bump structures located on a first side of the dielectric material layers, and die-side bump structures located on a second side of the dielectric material layers. A gap region is present between a first area including first die-side bump structures and a second area including second die-side bump structures. Stress-relief line structures are located on, or within, the dielectric material layers within an area of the gap region in the plan view. Each stress-relief line structures may include straight line segments that laterally extend along a respective horizontal direction and is not electrically connected to the redistribution interconnect structures. The stress-relief line structures may include the same material as, or may include a different material from, a metallic material of the redistribution interconnect structures or bump structures that are located at a same level.

Abstract: High performance modules for use in System-in-Package (SIP) devices, and methods of manufacture for such modules and SIPs. The modules employ one or more interposer substrates on which high performance components and/or devices are operatively mounted and interconnected.

Abstract: A semiconductor package includes a redistribution substrate and a semiconductor chip thereon. The redistribution substrate includes a ground under-bump pattern, signal under-bump patterns laterally spaced apart from the ground under-bump pattern, first signal line patterns disposed on the signal under-bump patterns and coupled to corresponding signal under-bump patterns, and a first ground pattern coupled to the ground under-bump pattern and laterally spaced apart from the first signal line pattern. Each of the signal and ground under-bump patterns includes a first part and a second part formed on the first part and that is wider than the first part. The second part of the ground under-bump pattern is wider than the second part of the signal under-bump pattern. The ground under-bump pattern vertically overlaps the first signal line patterns. The first ground pattern does not vertically overlap the signal under-bump patterns.

Abstract: Quantum dragon materials and devices have unit (total) transmission of electrons for a wide range of electron energies, even though the electrons do not undergo ballistic propagation, when connected optimally to at least two external leads. Quantum dragon materials and devices, as well as those that are nearly quantum dragons, enable embodiments as quantum dragon electronic or optoelectronic devices, including field effect transistors (FETs), sensors, injectors for spin-polarized currents, wires having integral multiples of the conductance quantum, and wires with zero electrical resistance. Methods of devising such quantum dragon materials and devices are also disclosed.

Abstract: An apparatus of fabricating a semiconductor device may include a chamber including a housing and a slit valve used to open or close a portion of the housing, a heater chuck provided in a lower region of the housing and used to heat a substrate, a target provided over the heater chuck, a plasma electrode provided in an upper region of the housing and used to generate plasma on the target, a heat-dissipation shield surrounding the inner wall of the housing between the plasma electrode and the heater chuck, and an edge heating structure provided between the heat-dissipation shield and the inner wall of the housing and configured to heat the heat-dissipation shield and an edge region of the substrate and to reduce a difference in temperature between center and edge regions of the substrate.

Abstract: A semiconductor package includes an encapsulated semiconductor device and a redistribution structure. The encapsulated semiconductor device includes a semiconductor device encapsulated by an encapsulating material. The redistribution structure overlays the encapsulated semiconductor device and includes a plurality of vias and a redistribution line. The plurality of vias are located on different layers of the redistribution structure respectively and connected to one another through a plurality of conductive lines, wherein, from a top view, an angle greater than zero is included between adjacent two of the plurality of conductive lines. The redistribution line is disposed under the plurality of conductive lines and connects corresponding one of the plurality of vias and electrically connected to the semiconductor device through the plurality of vias.

Abstract: Described are memory devices having stacked DRAM cells, resulting in an increase in DRAM cell bit-density. The area of a unit cell is composed of a capacitor, a cell transistor, an isolation region and a connection region, where every capacitor and active region for the cell capacitor is electrically isolated. The memory cells have supporting bars. Methods of forming a memory device are described. The methods include patterning the isolation region with supporting bars, removing non-insulator layers after isolation region patterning, and filling the opened region with an insulator.

Abstract: An electronic device includes a first part, and a circuit plate including a circuit substrate, a plating film made of a plating material and being disposed on a front surface of the substrate. The plating film includes a first part region on which the first part is disposed via a first solder, and a liquid-repellent region extending along a periphery side of the first part region in a surface layer of the plating film, and having a liquid repellency greater than a liquid repellency of the plating film. The liquid-repellent region includes a resist region. The plating film includes a remaining portion between the liquid-repellent region and the front surface of the circuit substrate in a thickness direction of the plating film orthogonal to the front surface. The remaining portion is made of the plating material and is free of the oxidized plating material.

Abstract: A chip on film package is disclosed, including a flexible film and a chip. The flexible film includes a film base, a patterned metal layer includes a plurality of pads and disposed on an upper surface of the film base, and a dummy metal layer covering a lower surface of the film base and capable of dissipating heat of the chip. The dummy metal layer comprises at least one opening exposing the second surface, and at least one of the plurality of pads is located within the at least one opening in a bottom view of the chip on film package. The chip is mounted on the plurality of pads of the patterned metal layer.

Abstract: Methods for manufacturing semiconductor devices having a flexible reinforcement structure, and associated systems and devices, are disclosed herein. In one embodiment, a method of manufacturing a semiconductor device includes electrically coupling at least one semiconductor die to a redistribution structure on a first carrier. The semiconductor die can include a first surface connected to the redistribution structure and a second surface spaced apart from the redistribution structure. The method also includes reducing a thickness of the semiconductor die to no more than 10 ?m. The method further includes coupling a flexible reinforcement structure to the second surface of the at least one semiconductor die.

Abstract: In one example, a semiconductor device comprises a first base substrate comprising a first base conductive structure, a first encapsulant contacting a lateral side of the first base substrate, a redistribution structure (RDS) substrate over the base substrate and comprising an RDS conductive structure coupled with the first base conductive structure, a first electronic component over the RDS substrate and over a first component terminal coupled with the RDS conductive structure, and a second encapsulant over the RDS substrate and contacting a lateral side of the first electronic component. Other examples and related methods are also disclosed herein.

Abstract: A semiconductor package includes a redistribution substrate having a dielectric layer and a wiring pattern in the dielectric layer, the wiring pattern including a line part that extends horizontally, and a via part connected to the line part, the via part having a width less than a width of the line part, a passivation layer on a top surface of the redistribution substrate, the passivation layer including a material different from a material of the dielectric layer, a conductive pillar that penetrates the passivation layer, the conductive pillar being connected to the via part, and a connection terminal on a top surface of the conductive pillar, a distance between the top surface of the conductive pillar and a top surface of the passivation layer being greater than a thickness of the passivation layer.

Abstract: Provided are compounds, formulations comprising compounds, and devices that utilize compounds, where the devices include a substrate, a first electrode, an organic emissive layer comprising an organic emissive material disposed over the first electrode. The device includes an enhancement layer, comprising a plasmonic material exhibiting surface plasmon resonance that non-radiatively couples to the organic emissive material and transfers excited state energy from the organic emissive material to the non-radiative mode of surface plasmon polaritons. The enhancement layer is provided no more than a threshold distance away from the organic emissive layer, where the organic emissive material has a total non-radiative decay rate constant and a total radiative decay rate constant due to the presence of the enhancement layer. At least one of the organic emissive material and the organic emissive layer has a vertical dipole ratio (VDR) value of equal or greater than 0.33.

Abstract: A semiconductor device, a circuit board structure and a manufacturing forming thereof are provided. A circuit board structure includes a core layer, a first build-up layer and a second build-up layer. The first build-up layer and the second build-up layer are disposed on opposite sides of the core layer. The circuit board structure has a plurality of stress releasing trenches extending into the first build-up layer and the second build-up layer.

Abstract: A semiconductor structure and a method of manufacturing a semiconductor structure are provided. The method includes forming a conductive layer on a precursor memory structure, in which the precursor memory structure includes a plurality of transistors and a plurality of contact plugs disposed on and connected to the transistors. The conductive layer in a TEG region is then patterned to form a first patterned conductive layer on the precursor memory structure. The first patterned conductive layer is then patterned to form a plurality of first landing pads extending along a first direction, in which the first landing pads are separated from each other in a second direction that is different from the first direction and are electrically connected to each other through the contact plugs and the transistors.

Abstract: A method used in forming integrated circuitry comprises forming conductive material over a substrate. The conductive material is patterned into a conductive line that is horizontally longitudinally elongated. The conductive material is vertically recessed in longitudinally-spaced first regions of the conductive line to form longitudinally-spaced conductive pillars that individually are in individual longitudinally-spaced second regions that longitudinally-alternate with the longitudinally-spaced first regions along the conductive line. The conductive pillars project vertically relative to the conductive material in the longitudinally-spaced and vertically-recessed first regions of the conductive line. Electronic components are formed directly above the conductive pillars. Individual of the electronic components are directly electrically coupled to individual of the conductive pillars. Additional methods, including structure independent of method, are disclosed.

Abstract: Provided is a display device including: a pixel unit in which a plurality of pixel circuits (PIX_A, PIX_B, PIX_C) each of which includes a light emitting element and a driving circuit configured to drive the light emitting element are arranged in a matrix form. In a diffusion layer in which transistors included in the driving circuits of the pixel circuits (PIX_A, PIX_B, PIX_C) are formed, an electricity supply region (223) that is an active area for supplying an electric potential to a well is provided between mutually adjacent ones of the pixel circuits (PIX_A, PIX_B, PIX_C).

Abstract: A package includes an integrated circuit. The integrated circuit includes a first chip, a second chip, a third chip, and a fourth chip. The second chip and the third chip are disposed side by side on the first chip. The second chip and the third chip are hybrid bonded to the first chip. The fourth chip is fusion bonded to at least one of the second chip and the third chip.

Abstract: A method used in forming an array of memory cells comprises forming lines of top-source/drain-region material, bottom-source/drain-region material, and channel-region material vertically there-between in rows in a first direction. The lines are spaced from one another in a second direction. The top-source/drain-region material, bottom-source/drain-region material, and channel-region material have respective opposing sides. The channel-region material on its opposing sides is laterally recessed in the second direction relative to the top-source/drain-region material and the bottom-source/drain-region material on their opposing sides to form a pair of lateral recesses in the opposing sides of the channel-region material in individual of the rows. After the pair of lateral recesses are formed, the lines of the top-source/drain-region material, the channel-region material, and the bottom-source/drain-region material are patterned in the second direction to comprise pillars of individual transistors.

Abstract: Microelectronic assemblies, related devices, and methods are disclosed herein. In some embodiments, a microelectronic assembly may include a die having a first surface and an opposing second surface; a capacitor having a surface, wherein the surface of the capacitor is coupled to the first surface of the die; and a conductive pillar coupled to the first surface of the die. In some embodiments, a microelectronic assembly may include a capacitor in a first dielectric layer; a conductive pillar in the first dielectric layer; a first die having a surface in the first dielectric layer; and a second die having a surface in a second dielectric layer, wherein the second dielectric layer is on the first dielectric layer, and wherein the surface of the second die is coupled to the capacitor, to the surface of the first die, and to the conductive pillar.