Abstract: A method includes forming a redistribution structure, which formation process includes forming a plurality of dielectric layers over a carrier, forming a plurality of redistribution lines extending into the plurality of dielectric layers, and forming a reinforcing patch over the carrier. The method further includes bonding a package component to the redistribution structure, with the package component having a peripheral region overlapping a portion of the reinforcing patch. And de-bonding the redistribution structure and the first package component from the carrier.

Abstract: A semiconductor structure includes an encapsulated die including an electronic die and an insulating layer laterally covering the electronic die, and a photonic die coupled to the encapsulated die. The photonic die includes an optical device in proximity to an edge coupling facet of a portion of a sidewall of the photonic die, wherein a surface roughness of the edge coupling facet is less than a surface roughness of a sidewall of the insulating layer or a surface roughness of another portion of the sidewall of the photonic die.

Abstract: A method of manufacturing a semiconductor device includes placing a polymer raw material mixture over a substrate. The polymer raw material may include a polymer precursor, a photosensitizer, and an additive. The polymer raw material mixture is exposed to radiation to form a dielectric layer and cured at a temperature of between about 150° C. and about 230° C.

Abstract: Microelectronic assemblies, related devices, and methods are disclosed herein. In some embodiments, a microelectronic assembly may include a die having a first surface and an opposing second surface; a capacitor having a surface, wherein the surface of the capacitor is coupled to the first surface of the die; and a conductive pillar coupled to the first surface of the die. In some embodiments, a microelectronic assembly may include a capacitor in a first dielectric layer; a conductive pillar in the first dielectric layer; a first die having a surface in the first dielectric layer; and a second die having a surface in a second dielectric layer, wherein the second dielectric layer is on the first dielectric layer, and wherein the surface of the second die is coupled to the capacitor, to the surface of the first die, and to the conductive pillar.

Abstract: In a semiconductor device, a first stack is positioned over substrate and includes a first pair of transistors and a second pair of transistors stacked over the substrate. A second stack is positioned over the substrate and adjacent to the first stack. The second stack includes a third pair of transistors and a fourth pair of transistors stacked over the substrate. A first capacitor is stacked with the first and second stacks. A second capacitor is positioned adjacent to the first capacitor and stacked with the first and second stacks. A first group of the transistors in the first and second stacks is coupled to each other to form a static random-access memory cell. A second group of the transistors in the first and second stacks is coupled to the first and second capacitors to form a first dynamic random-access memory (DRAM) cell and a second DRAM cell.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure includes a first substrate having an upper surface and a recessed surface extending in a closed loop around the upper surface. The recessed surface is vertically between the upper surface and a lower surface of the first substrate opposing the upper surface. A first plurality of interconnects are disposed within a first dielectric structure on the upper surface. A dielectric protection layer is over the recessed surface, along a sidewall of the first dielectric structure, and along a sidewall of the first substrate. The first substrate extends from directly below the dielectric protection layer to laterally outside of the dielectric protection layer.

Abstract: A semiconductor package includes a first die comprising an upper surface and a lower surface opposite to the upper surface. The first die includes a plurality of through-silicon vias (TSVs) penetrating through the first die. A second die is stacked on the upper surface of the first die. An interposer layer is disposed on the lower surface of the first die. An inductor is disposed in the interposer layer. The inductor comprises terminals directly coupled to the TSVs.

Abstract: A semiconductor package includes a substrate and a semiconductor chip disposed over the substrate. The substrate includes: a base layer including an upper surface facing the semiconductor chip; an upper ground electrode plate disposed over the upper surface of the base layer and configured to transmit a ground voltage to the semiconductor chip; and a dummy power pattern disposed in the upper ground electrode plate and having a side surface which is surrounded by the upper ground electrode plate and is spaced apart from the upper ground electrode plate with an insulating material between the dummy power pattern and the upper ground electrode plate. A ground voltage transmission path from the upper ground electrode plate to the semiconductor chip is spaced apart from the dummy power pattern.

Abstract: A packaged integrated circuit device includes a substrate having a spacer chip thereon, which is devoid of active integrated circuits therein but which has a stress-relieving pattern of grooves in an upper surface thereof. A first semiconductor chip is provided, which is bonded to the upper surface of the spacer chip. A molded region is provided, which includes a passivating resin that: (i) at least partially surrounds the first semiconductor chip and the spacer chip, and (ii) extends into at least a portion of the grooves within the upper surface of the spacer chip.

Abstract: A method used in forming a memory array and conductive through-array-vias (TAVs) comprises forming a stack comprising vertically-alternating insulative tiers and wordline tiers. A mask is formed comprising horizontally-elongated trench openings and operative TAV openings above the stack. Etching is conducted of unmasked portions of the stack through the trench and operative TAV openings in the mask to form horizontally-elongated trench openings in the stack and to form operative TAV openings in the stack. Conductive material is formed in the operative TAV openings in the stack to form individual operative TAVs in individual of the operative TAV openings in the stack. A wordline-intervening structure is formed in individual of the trench openings in the stack.

Abstract: Methods/structures of joining package structures are described. Those methods/structures may include a die disposed on a surface of a substrate, wherein the die comprises a plurality of high density features. An interconnect bridge is embedded in the substrate, wherein the interconnect bridge may comprise a first region disposed on a surface of the interconnect bridge comprising a first plurality of features, wherein the first plurality of features comprises a first pitch. A second region disposed on the surface of the interconnect bridge comprises a second plurality of features comprising a second pitch, wherein the second pitch is greater than the first pitch.

Abstract: Memory devices and methods of manufacturing memory devices are provided. Described are devices and methods where 3D pitch multiplication decouples high aspect ratio etch width from cell width, creating small cell active area pitch to allow for small DRAM die size.

Abstract: A semiconductor package includes a photonic integrated circuit, an electronic integrated circuit and a waveguide. The photonic integrated circuit includes an optical coupler. The electronic integrated circuit is disposed aside the photonic integrated circuit. The waveguide is optically coupled to the optical coupler, wherein the waveguide is disposed at an edge of the photonic integrated circuit and protrudes from the edge of the photonic integrated circuit.

Abstract: Disclosed are interconnection structures, semiconductor packages including the same, and methods of fabricating the same.

Abstract: A metal-insulator-metal (MIM) capacitor structure includes a bottom electrode, a first oxide layer adjacent the bottom electrode, and a first high-k dielectric layer over the bottom electrode and the first oxide layer. A middle electrode is over the first high-k dielectric layer and a second oxide layer is adjacent the middle electrode. A second high-k dielectric layer may be over the middle electrode and the second oxide layer, a top electrode may be over the second high-k dielectric layer.

Abstract: The present disclosure relates to a memory device. The memory device includes an access device arranged on or within a substrate and coupled to a word-line and a source line. A plurality of lower interconnects are disposed within a lower dielectric structure over the substrate. A first electrode is coupled to the plurality of lower interconnects. The plurality of lower interconnects couple the access device to the first electrode. A second electrode is over the first electrode. One or more upper interconnects are disposed within an upper dielectric structure laterally surrounding the second electrode. The one or more upper interconnects couple the second electrode to a bit-line. A data storage structure is disposed between the first electrode and the second electrode. The data storage structure includes one or more metals having non-zero concentrations that change as a distance from the substrate varies.

Abstract: A semiconductor package may include a redistribution substrate having a first surface and a second surface, opposite to each other, a semiconductor chip on the first surface of the redistribution substrate, and a solder pattern on the second surface of the redistribution substrate. The redistribution substrate may include an under-bump pattern coupled to the solder pattern, a first redistribution pattern on the under-bump pattern, the first redistribution pattern including a first via portion and a first wire portion, and a first seed pattern between the under-bump pattern and the first redistribution pattern and on a side surface of the first via portion and a bottom surface of the first wire portion. A bottom surface of the first seed pattern may be at a level lower than a top surface of the under-bump pattern.

Abstract: A device including a stack of layers defining a first conductor pattern at a first level of the stack and one or more semiconductor channels in respective regions, connecting a pair of parts of the first conductor pattern, and capacitively coupled via a dielectric to a coupling conductor of a second conductor pattern at a second level of the stack. The stack includes at least two insulator patterns over which the first level or second level conductor patterns is formed. A first insulator pattern occupies one or more semiconductor channel regions to provide the dielectric. The second insulator pattern defines one or more windows in the one or more semiconductor channel regions through which the second conductor pattern contacts the first insulator pattern other than via the second insulator pattern. The second insulator pattern overlaps the first insulator pattern outside the one or more semiconductor channel regions.

Abstract: Apparatuses may include a device substrate including a microelectronic device and bond pads proximate to an active surface of the device substrate. A package substrate may be secured to the device substrate, the package substrate configured to route signals to and from the bond pads. A ball grid array may be supported on, and electrically connected to, the package substrate. Each ball positioned and configured to carry a high-bandwidth data signal or a high-frequency clock signal may be located laterally or longitudinally adjacent to no more than one other ball of the ball grid array configured to carry a high-bandwidth data signal or a high-frequency clock signal. Each ball positioned and configured to carry a high-bandwidth data signal may be located only diagonally adjacent to any other balls configured to carry a high-bandwidth data signal or a high-frequency clock signal.

Abstract: A semiconductor memory device includes a semiconductor substrate, a first insulating film provided above the semiconductor substrate, a first conductive film provided above the first insulating film, a plurality of first electrode films provided above the first conductive film and stacked to be separated from each other, a semiconductor member extending in a stacking direction of the plurality of first electrode films, and a charge storage member provided between the semiconductor member and one of the plurality of first electrode films. The first conductive film includes a main portion disposed at least below the plurality of first electrode films, and a fine line portion extending from the main portion toward an end surface side of the semiconductor substrate. A width of the fine line portion is narrower than a width of the main portion.