Patents Examined by Niki H Nguyen
  • Semiconductor device package and method of manufacturing the same
    Patent number: 11329015
    Abstract: A semiconductor device package includes an emitting device and a first building-up circuit. The emitting device defines a cavity in the emitting device. The first building-up circuit is disposed on the emitting device.
    Type: Grant
    Filed: February 12, 2020
    Date of Patent: May 10, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Meng-Wei Hsieh
  • Integrated circuit device
    Patent number: 11329057
    Abstract: An integrated circuit device includes a memory including a memory cell insulation surrounding a memory stack and a memory cell interconnection unit, a peripheral circuit including a peripheral circuit region formed on a peripheral circuit board, and a peripheral circuit interconnection between the peripheral circuit region and the memory structure, a plurality of conductive bonding structures on a boundary between the memory cell interconnection and the peripheral circuit interconnection in a first region, the first region overlapping the memory stack in a vertical direction, and a through electrode penetrating one of the memory cell insulation and the peripheral circuit board and extended to a lower conductive pattern included in the peripheral circuit interconnection in a second region, the second region overlapping the memory cell insulation in the vertical direction.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: May 10, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chanho Kim, Dongku Kang, Daeseok Byeon
  • High frequency module
    Patent number: 11309259
    Abstract: A high frequency module in which warpage does not easily occur is provided by adjusting linear expansion coefficient, glass transition temperature, and elastic modulus of a sealing resin layer. The high frequency module includes a wiring board, a first component mounted on a lower surface of the wiring board, a plurality of connection terminals, a first sealing resin layer that coats the first component and the connection terminal, a plurality of second components mounted on an upper surface of the wiring board, a second sealing resin layer coating the second components, and a shield film. The first sealing resin layer is formed thinner than the second sealing resin layer, and the first sealing resin layer has the linear expansion coefficient of the resin smaller than the linear expansion coefficient of the resin of the second sealing resin layer.
    Type: Grant
    Filed: October 22, 2020
    Date of Patent: April 19, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Tadashi Nomura, Takafumi Kusuyama
  • Electromigration resistant and profile consistent contact arrays
    Patent number: 11309239
    Abstract: A package assembly includes a substrate and at least a first die having a first contact array and a second contact array. First and second via assemblies are respectively coupled with the first and second contact arrays. Each of the first and second via assemblies includes a base pad, a cap assembly, and a via therebetween. One or more of the cap assembly or the via includes an electromigration resistant material to isolate each of the base pad and the cap assembly. Each first cap assembly and via of the first via assemblies has a first assembly profile less than a second assembly profile of each second cap assembly and via of the second via assemblies. The first and second cap assemblies have a common applied thickness in an application configuration. The first and second cap assemblies have a thickness variation of ten microns or less in a reflowed configuration.
    Type: Grant
    Filed: October 20, 2020
    Date of Patent: April 19, 2022
    Assignee: Intel Corporation
    Inventors: Srinivas Pietambaram, Jung Kyu Han, Ali Lehaf, Steve Cho, Thomas Heaton, Hiroki Tanaka, Kristof Darmawikarta, Robert Alan May, Sri Ranga Sai Boyapati
  • Chip package structure with conductive adhesive layer and method for forming the same
    Patent number: 11302537
    Abstract: A method for forming a chip package structure is provided. The method includes providing a wiring substrate including a substrate, a pad, and a polymer layer. The polymer layer is over the substrate and the pad, and the polymer layer has a first opening exposing the pad. The method includes forming a conductive adhesive layer over the polymer layer and the pad. The conductive adhesive layer is in direct contact with and conformally covers the polymer layer and the pad. The method includes forming a nickel layer over the conductive adhesive layer. The nickel layer is thicker than the conductive adhesive layer, and the nickel layer and the conductive adhesive layer are made of different materials. The method includes bonding a chip to the wiring substrate through a conductive bump. The conductive bump is between the nickel layer and the chip.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: April 12, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Ching Hsu, Yu-Huan Chen, Chen-Shien Chen
  • Semiconductor device and method of manufacturing the same
    Patent number: 11296045
    Abstract: A semiconductor device is provided and includes first and second semiconductor chips bonded together. The first chip includes a first substrate, a first insulating layer disposed on the first substrate and having a top surface, a first metal pad embedded in the first insulating layer and having a top surface substantially planar with the top surface of the first insulating layer, and a first barrier disposed between the first insulating layer and the first metal pad. The second chip includes a second substrate, a second insulating layer, a second metal pad, and a second barrier with a similar configuration to the first chip. The top surfaces of the first and second insulating layers are bonded to provide a bonding interface, the first and second metal pads are connected, and a portion of the first insulating layer is in contact with a side region of the first metal pad.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: April 5, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Joohee Jang, Seokho Kim, Hoonjoo Na, Jaehyung Park, Kyuha Lee
  • Die-to-wafer bonding structure and semiconductor package using the same
    Patent number: 11289438
    Abstract: According to an aspect of the inventive concept, there is provided a die-to-wafer bonding structure including a die having a first test pad, a first bonding pad formed on the first test pad, and a first insulating layer, the first bonding pad penetrates the first insulating layer. The structure may further include a wafer having a second test pad, a second bonding pad formed on the second test pad, and a second insulating layer, the second bonding pad penetrates the second insulating layer. The structure may further include a polymer layer surrounding all side surfaces of the first bonding pad and all side surfaces of the second bonding pad, the polymer layer being arranged between the die and the wafer. Additionally, the wafer and the die may be bonded together.
    Type: Grant
    Filed: August 5, 2020
    Date of Patent: March 29, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jiseok Hong, Unbyoung Kang, Myungsung Kang, Taehun Kim, Sangcheon Park, Hyuekjae Lee, Jihwan Hwang
  • Semiconductor package and method of manufacturing the same
    Patent number: 11282777
    Abstract: A semiconductor package includes a core layer, a conductive interconnect and a semiconductor chip. The core layer has a top surface and a bottom surface opposite to the top surface. The conductive interconnect penetrates through the core layer. The conductive interconnect has a top surface and a bottom surface respectively exposed from the top surface and the bottom surface of the core layer. The semiconductor chip is disposed on the top surface of the core layer. The semiconductor chip includes a conductive pad, and the top surface of the conductive interconnect directly contacts the conductive pad.
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: March 22, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: You-Lung Yen, Bernd Karl Appelt
  • Oversized via as through-substrate-via (TSV) stop layer
    Patent number: 11282769
    Abstract: The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure includes a standard via disposed on a first side of a substrate. An oversized via is disposed on the first side of the substrate and is laterally separated from the standard via. The oversized via has a larger width than the standard via. An interconnect wire vertically contacting the oversized via. A through-substrate via (TSV) extends from a second side of the substrate, and through the substrate, to physically contact the oversized via or the interconnect wire. The TSV has a minimum width that is smaller than a width of the oversized via.
    Type: Grant
    Filed: June 11, 2020
    Date of Patent: March 22, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Hsing-Chih Lin, Jen-Cheng Liu, Yi-Shin Chu, Ping-Tzu Chen
  • Light emitting device and light source
    Patent number: 11282990
    Abstract: A light emitting device includes at least one first light emitting element to emit a first light having a first peak emission wavelength in a range of 370 nm or greater and 415 nm or less, and at least one fluorescent material to convert the first light to a second light having a second peak wavelength in a range of 550 nm or greater and to 780 nm or less. In an emission spectrum of the light emitting device, a ratio of an intensity of the first peak emission wavelength to a maximum intensity of the second peak emission wavelength is in a range of 0.005 to 0.20.
    Type: Grant
    Filed: July 1, 2020
    Date of Patent: March 22, 2022
    Assignee: NICHIA CORPORATION
    Inventor: Taiki Yuasa
  • Light emitting structure and solar photovoltaic power generation system
    Patent number: 11276804
    Abstract: The light emitting structure of the present invention includes a sheet-shaped structure which absorbs excitation light and emits light with wavelength conversion and which has a maximum emission wavelength of 400 nm or more; and an antireflection material provided on a side surface of the sheet-shaped structure.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: March 15, 2022
    Assignee: SEKISUI CHEMICAL CO., LTD.
    Inventors: Shougo Yoshida, Yuusuke Oota, Yasuyuki Izu, Daizou Ii, Masaki Matsudou, Kinryou Chou, Daisuke Nakajima
  • System and method for providing mechanical isolation of assembled diodes
    Patent number: 11270983
    Abstract: A circuit, comprising a diode, a conductive upper support disposed on top of the diode and electrically coupled to the diode, a conductive lower support disposed underneath the diode and electrically coupled to the diode, a mechanical support disposed adjacent to the diode, the conductive upper support and the conductive lower support, an insulator disposed underneath the mechanical support, an upper terminal coupled to the mechanical support and electrically coupled to the conductive upper support and a lower terminal coupled to the insulator and electrically coupled to the conductive lower support.
    Type: Grant
    Filed: October 14, 2019
    Date of Patent: March 8, 2022
    Assignee: SEMTECH CORPORATION
    Inventors: David Francis Courtney, Angel Mario Cano Garza
  • Semiconductor wafer and method of probe testing
    Patent number: 11257724
    Abstract: Implementations of methods of making a semiconductor device may include: providing a partial semiconductor wafer. The method may also include providing a wafer holder including a tape portion with one or more openings through the tape portion. The method may include mounting the partial semiconductor wafer over the one or more openings in the tape portion of the wafer holder and providing an electrical connection to the partial semiconductor wafer through the one or more openings in the tape portion during probe test.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: February 22, 2022
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Michael J. Seddon
  • Cascode semiconductor device and method of manufacture
    Patent number: 11227819
    Abstract: This disclosure relates to a discrete semiconductor device and associated method of manufacture, the discrete semiconductor device includes: a high voltage depletion mode device die; and a low voltage enhancement mode device die connected in cascode configuration with the high voltage depletion mode device die. The high voltage depletion mode device includes a gate, source and drain terminals arranged on a first surface thereof and the gate source and drain terminals are inverted with respect to the low voltage enhancement mode device die and the low voltage device is arranged adjacent to the high voltage device.
    Type: Grant
    Filed: January 28, 2020
    Date of Patent: January 18, 2022
    Assignee: Nexperia B.V.
    Inventors: Robert James Montgomery, Ricardo Lagmay Yandoc
  • Semiconductor package having enlarged gate pad and method of making the same
    Patent number: 11222858
    Abstract: A semiconductor package fabrication method comprises the steps of providing a wafer, applying a seed layer, forming a photo resist layer, plating a copper layer, removing the photo resist layer, removing the seed layer, applying a grinding process, forming metallization, and applying a singulation process. A semiconductor package comprises a silicon layer, an aluminum layer, a passivation layer, a polyimide layer, a copper layer, and metallization. In one example, an area of a contact area of a gate clip is smaller than an area of a gate copper surface. The area of the contact area of the gate clip is larger than a gate aluminum surface. In another example, an area of a contact area of a gate pin is larger than an area of a gate copper surface. The area of the contact area of the gate pin is larger than a gate aluminum surface.
    Type: Grant
    Filed: June 19, 2020
    Date of Patent: January 11, 2022
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LP
    Inventors: Yan Xun Xue, Yueh-Se Ho, Long-Ching Wang, Xiaotian Zhang, Zhiqiang Niu
  • Package and manufacturing method thereof
    Patent number: 11222867
    Abstract: A package includes a first die, a second die, a semiconductor frame, and a reinforcement structure. The first di has a first surface and a second surface opposite to the first surface. The first die includes grooves on the first surface. The second die and the semiconductor frame are disposed side by side over the first surface of the first die. The semiconductor frame has at least one notch exposing the grooves of the first die. The reinforcement structure is disposed on the second surface of the first die. The reinforcement structure includes a first portion aligned with the grooves.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: January 11, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sung-Hui Huang, Shang-Yun Hou, Kuan-Yu Huang
  • Zero-misalignment two-via structures
    Patent number: 11222836
    Abstract: Device package and a method of forming a device package are described. The device package includes an interposer with interconnects on an interconnect package layer and a conductive layer on the interposer. The device package has dies on the conductive layer, where the package layer includes a zero-misalignment two-via stack (ZM2VS) and a dielectric. The ZM2VS directly coupled to the interconnect. The ZM2VS further includes the dielectric on a conductive pad, a first via on a first seed, and first seed on a top surface of the conductive pad, where the first via extends through dielectric. The ZM2VS also has a conductive trace on dielectric, and a second via on a second seed, the second seed is on the dielectric, where the conductive trace connects to first and second vias, where second via connects to an edge of conductive trace opposite from first via.
    Type: Grant
    Filed: December 30, 2017
    Date of Patent: January 11, 2022
    Assignee: Intel Corporation
    Inventors: Veronica Strong, Aleksandar Aleksov, Brandon Rawlings, Johanna Swan
  • Variable resistance semiconductor device having oxidation-resistant electrode
    Patent number: 11223012
    Abstract: A variable resistance semiconductor device includes a lower conductive wiring; a bottom electrode over the lower conductive wiring; a selection element pattern over the bottom electrode; a first intermediate electrode over the selection element pattern; a second intermediate electrode over the first intermediate electrode; a variable resistance element pattern over the second intermediate electrode; a top electrode over the variable resistance element pattern; and an upper conductive wiring over the top electrode. The first intermediate electrode includes a first material. The second intermediate electrode includes a second material which has a better oxidation resistance and a higher work function than the first material.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: January 11, 2022
    Assignee: SK hynix Inc.
    Inventors: Woo-Young Park, Young-Seok Ko, Soo-Gil Kim
  • Light emitting structure to aid LED light extraction
    Patent number: 11217567
    Abstract: Display panels and methods of manufacture are described for down converting a peak emission wavelength of a pump LED within a subpixel with a quantum dot layer. In some embodiments, pump LEDs with a peak emission wavelength below 500 nm, such as between 340 nm and 420 nm are used. QD layers in accordance with embodiments can be integrated into a variety of display panel structures including a wavelength conversion cover arrangement, QD patch arrangement, or QD layers patterned on the display substrate.
    Type: Grant
    Filed: April 28, 2020
    Date of Patent: January 4, 2022
    Inventors: Jonathan S. Steckel, Jean-Jacques P. Drolet, Roland Van Gelder, Kelly C. McGroddy, Ion Bita, James Michael Perkins, Andreas Bibl, Sajjad A. Khan, James E. Pedder, Elmar Gehlen
  • Organic mold interconnects in shielded interconnects frames for integrated-circuit packages
    Patent number: 11205613
    Abstract: A molded frame interconnect includes power, ground and signal frame interconnects in a molded mass, that encloses an integrated-circuit package precursor, which is inserted into the frame, and coupled to the frame interconnects by a build-up redistribution layer.
    Type: Grant
    Filed: June 25, 2020
    Date of Patent: December 21, 2021
    Assignee: Intel Corporation
    Inventors: Jiun Hann Sir, Eng Huat Goh, Poh Boon Khoo