Abstract: Subject matter disclosed herein may relate to fabrication of a correlated electron material (CEM) device. In embodiments, after formation of the one or more CEM traces, a spacer may be deposited in contact with the one or more CEM traces. The spacer may operate to control an atomic concentration of dopant within the one or more CEM traces by replenishing dopant that may be lost during subsequent processing and/or by forming a seal to reduce further loss of dopant from the one or more CEM traces.

Abstract: A display device includes a display area, a test pad, a plurality of first test transistors, and at least one outline. The display area includes pixels coupled to data lines and scan lines. The test pad receives a test signal. The first test transistors are coupled between the data lines of the display area and the test pad. The at least one outline is coupled between one of the first test transistors and the test pad. The at least one outline is located in a non-display area outside the display area.

Abstract: Disclosed are structures and methods related to metallization of a gallium arsenide (GaAs) layer. In some embodiments, a tantalum nitride (TaN) layer can be formed on a doped GaAs layer, and a metal layer can be formed on the TaN layer. Such a structure can be included in a Schottky diode. In some embodiments, such a Schottky diode can be fabricated utilizing heterojunction bipolar transistor (HBT) processes.

Abstract: The present disclosure provides a method for manufacturing a semiconductor structure. The semiconductor structure includes a substrate; a pad disposed over the substrate; a first passivation disposed over the substrate, partially covering the pad, and including a protrusion protruded from the first passivation and away from the substrate; a conductive layer disposed over the first passivation and a portion of the pad exposed from the first passivation; and a second passivation disposed over the conductive layer, wherein the conductive layer disposed over the protrusion is exposed from the second passivation.

Abstract: A semiconductor light-emitting device including at least a substrate, a reflector having a concave cavity, and an optical semiconductor element, wherein the reflector is formed of a resin composition containing an inorganic substance; in a spectrum obtained when the reflector is measured by an X-ray diffraction method using CuK? radiation (wavelength=1.5418 A), an intensity ratio (P1/P2) of a peak intensity P1 of the highest intensity diffraction peak in a range of diffraction angle 2? of 0° to 24° to the peak intensity P2 of the highest intensity diffraction peak in a range of diffraction angle 2? of more than 24° to 70° is 0.01 or more and 1.0 or less; and an ash content of the reflector is 60% by mass or more. A semiconductor light-emitting device and an optical-semiconductor-mounting substrate, including a reflector having an extremely high light reflection property and excellent dimensional stability.

Abstract: A ?LED device comprising: a substrate and an epitaxial layer grown on the substrate and comprising a semiconductor material, wherein at least a portion of the substrate and the epitaxial layer define a mesa; an active layer within the mesa and configured, on application of an electrical current, to generate light for emission through a light emitting surface of the substrate opposite the mesa, wherein the crystal lattice structure of the substrate and the epitaxial layer is arranged such that a c-plane of the crystal lattice structure is misaligned with respect to the light emitting surface.

Abstract: A semiconductor device includes a semiconductor chip having an active surface having connection pads disposed thereon; an encapsulant encapsulating at least portions of the semiconductor chip, a connection member disposed on the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads, a passivation layer disposed on the connection member, and an under bump metallurgy (UBM) layer embedded in the passivation layer and electrically connected to the redistribution layer of the connection member. The UBM layer includes a UBM pad embedded in the passivation layer and having a recess portion, and a UBM via penetrating through a portion of the passivation layer and electrically connecting the redistribution layer of the connection member and the UBM pad to each other.

Abstract: A semiconductor device includes a first metal plate and a second metal plate which interpose a first semiconductor element therebetween, the first metal plate and the second metal plate being bonded to the first semiconductor element with first soldered portions; and includes a third metal plate and a fourth metal plate which interpose a second semiconductor element therebetween, the third metal plate and the fourth metal plate being bonded to the second semiconductor element with second soldered portions. A first joint provided at an edge of the first metal plate and a second joint provided at an edge of the fourth metal plate are bonded with a third soldered portion. A total sum of thicknesses of the first soldered portions is different from a thickness of the third soldered portion, a solidifying point of the thinner one is higher than a solidifying point of the thicker one.

Abstract: Processes for manufacturing cellulose based integrated circuitry constructions are provided, the processes can include providing a first substrate having a plurality of vias; providing a first conductive material to the one surface of the substrate; providing adhesive to the other surface; providing a monolithic electronic component to the other surface; providing a second conductive material to the other surface and the monolithic electronic component; providing a backing material to the other surface of the substrate; and providing a second substrate to the backing material to form the construction.

Abstract: The present invention discloses an organic electroluminescent display device and a display apparatus, wherein the organic electroluminescent display device employs an optical film lamination as a base substrate or a packaging cover plate, the optical film lamination includes a circular polarizer film, a water-oxygen resistant film and a color resistant film that are located on a supporting substrate, thus it has an antireflection function, a good water-oxygen resistance as well as a full-color display function, so that not only the problem of fussy process and high cost of an OLED display device caused by film application can be solved, but also the problem that the thickness of a flexible OLED display device is increased and thus the device is difficult to be rolled up due to film application is avoided; also, the OLED display device has the advantages of being lighter and thinner and having a better display effect, etc.

Abstract: A method is provided that includes forming a first vertically-oriented transistor above a substrate, the first vertically-oriented transistor comprising a first sidewall gate disposed in a first direction, forming a second vertically-oriented transistor above the substrate, the second vertically-oriented transistor including a second sidewall gate disposed in the first direction, and forming an air gap chamber above the substrate disposed between the first sidewall gate and the second sidewall gate, and extending in the first direction, the air gap chamber including an air gap.

Abstract: A semiconductor device comprises non-quadrangular metal regions in the last metallization layer and/or non-quadrangular contact pads, wherein, in some illustrative embodiments, an interdigitating lateral configuration may be obtained and/or an overlap of the contact pads with underlying metal regions may be provided. Consequently, mechanical robustness of the contact pads and the passivation material under the underlying interlayer dielectric material may be increased, thereby suppressing crack formation and crack propagation.

Abstract: Some embodiments of the present disclosure provide an optical sensor. The optical sensor includes a semiconductive block having a front side and a back side, a wave guide region, and a light sensing region. The wave guide region is positioned over the back side of the semiconductive block and having a core layer. The wave guide region is configured to guide an incident light. The light sensing region is positioned in the semiconductive block, having a multi-junction photodiode. The light sensing region is configured to sense emission lights from the wave guide region.

Abstract: Aspects of the disclosure include a method for making a semiconductor, including patterning a first transistor having one or more gate stacks on a first source-drain area and second transistor comprising one or more gate stacks on a second source-drain area, forming dielectric spacers on gate stack side walls, depositing a first nitride liner on the first and second transistors. The method also includes masking the second transistor and etching to remove the first nitride material and the spacer from the first source-drain area and growing a first epitaxial layer on the first source-drain area by an epitaxial growth process. The method also includes depositing a second nitride liner on the first and second transistors. The method also includes masking the first transistor. The method also includes etching to remove the second nitride material from the second source-drain area and growing a second epitaxial layer on the second source-drain area by an epitaxial growth process.

Abstract: A transistor having favorable electrical characteristics. A transistor suitable for miniaturization. A transistor having a high switching speed. One embodiment of the present invention is a semiconductor device that includes a transistor. The transistor includes an oxide semiconductor, a gate electrode, and a gate insulator. The oxide semiconductor includes a first region in which the oxide semiconductor and the gate electrode overlap with each other with the gate insulator positioned therebetween. The transistor has a threshold voltage higher than 0 V and a switching speed lower than 100 nanoseconds.

Abstract: A converter material includes a porous inorganic matrix material having a multiplicity of pores. A multiplicity of inorganic nanoparticles are applied on the surface of the matrix material. The nanoparticles are suitable for converting electromagnetic radiation in a first wavelength range into electromagnetic radiation in a second wavelength range. A method for producing such a converter material and an optoelectronic component that includes such a converter material are furthermore specified.

Abstract: A semiconductor structure includes a substrate, a first fin structure disposed over the substrate, a second fin structure disposed over the substrate, and an isolation structure disposed between the first fin structure and the second fin structure and electrically isolating the first fin structure from the second fin structure. The isolation structure includes a first thickness, a second thickness and a third thickness different from each other.

Abstract: A semiconductor device includes a semiconductor substrate comprising a group III element and a group V element, and a gate structure on the semiconductor substrate. The semiconductor substrate includes a first region which contacts a bottom surface of the gate structure and a second region which is disposed under the first region. The concentration of the group III element in the first region is lower than that of the group V element in the first region, and the concentration of the group III element in the second region is substantially equal to that of the group V element in the second region.

Abstract: A variable resistance memory device includes a plurality of first conductive lines, each of the first conductive lines extends in a first direction, a plurality of second conductive lines are above the first conductive lines, and each of the second conductive lines extend in a second direction transverse to the first direction. A plurality of first memory cells are at intersections where the first and second conductive lines overlap each other, each of the first memory cells including a first variable resistance structure having a first variable resistance pattern, a first sacrificial pattern and a second variable resistance pattern sequentially stacked in the first direction on a first plane. A plurality of third conductive lines are above the second conductive lines, each of the third conductive lines extend in the first direction, and a plurality of second memory cells are at intersections where the second and the third conductive lines overlap each other.

Abstract: A display device is disclosed. In one aspect, a plurality of pixels are formed in a display area, and the pixels include a first pixel including a thin film transistor (TFT). The display device includes a test unit formed in a peripheral area surrounding the display area, and the test unit includes a test transistor configured to measure a characteristic of the TFT included in the first pixel. The display device also includes a first insulating layer formed over the test transistor and the display area, and a plurality of dummy contact holes are formed in the first insulating layer and the test unit.