Abstract: An alarm detect unit (a path switching apparatus) for selecting an active path comprises a path-alarm detect circuit and a guard timer for a working path as well as a path-alarm detect circuit and a guard timer for a protection path. When an alarm is detected on the active path, alarm information, that is, information on the generation of the alarm, is delayed by a predetermined time by the guard timer of the working or protection path that serves as the active path.By the same token, when an alarm is detected on a standby path, alarm information, that is, information on the recovery of the alarm, is delayed by a predetermined time by the guard timer of the working or protection path that serves as the standby path. Either the working or protection path is then selected as the active path in accordance with pieces of alarm information output by the two guard timers which indicate the line-failure-occurrence states of the active and standby paths.

Abstract: In a first aspect, a method of synchronizing at least two computing elements that each have clocks that operate asynchronously of the clocks of the other computing elements includes selecting one or more signals, designated as meta time signals, from a set of signals produced by the computing elements, monitoring the computing elements to detect the production of a selected signal by one of the computing elements, waiting for the other computing elements to produce a selected signal, transmitting equally valued time updates to each of the computing elements, and updating the clocks of the computing elements based on the time updates.In a second aspect, fault resilient or fault tolerant computers are produced by designating a first processor as a computing element, designating a second processor as a controller, connecting the computing element and the controller to produce a modular pair, and connecting at least two modular pairs to produce a fault resilient or fault tolerant computer.

Abstract: An apparatus for tracking processing of commands between command sources and sinks includes a command directory. The command directory receives a command from at least one command source, receives signals from command sinks, generates status information corresponding to the command based on the command and the received signals, and stores the status information. The status information indicates to which command sink the command is to be routed, whether the command sink has accepted the command, and whether the command sink has completed processing the command. The command directory includes a command buffer having a plurality of directory entries. The command buffer stores a command and associated status information in a directory entry. The command buffer also includes free buffer logic which monitors the status information in each directory entry. Based on this monitoring, the free buffer logic determines whether a directory entry has been disabled or whether command tracking errors exist.

Abstract: In a system for taking over data of the present invention, a first data processing unit processes a processing data following an execution of a program. A second data processing unit transfers a takeover data necessary for resuming a process from the first data processing unit, when there is some trouble with the first data processing unit. A volatile storage unit stores the takeover data and the processing data to be processed by the first data processing unit. A change unit changes the takeover data stored in the volatile storage unit into a new takeover data following the execution of the program by the first data processing unit. A nonvolatile storage unit is connected to the first data processing unit and the second data processing unit, and stores the takeover data. A demanding unit issues a transmission demand for transmitting the processing data stored in the volatile storage unit to one of the nonvolatile storage unit and a network.

Abstract: A parallel, fault-tolerant computer system in which data is transferred between processes in a single CPU by two methods. In a first method, the data is copied each time it is transferred. In a second method, the data is not copied, but is passed through a shared memory, queueing system. The first method is used to ensure fault-tolerance and linear expandability. The second method is used to minimize the time required for inter-process communication. Use of the shared memory queueing system allows for increased vertical and horizontal modularity for processes executing in a same CPU.

Abstract: An on-chip testing device separately locates must-repairs or preferred-repairs in a row direction and column direction of a memory array. A row counter and a column counter are operated to index the memory array in row-major order, and then in column-major order (or vice versa). A running total of the number of failures is kept for each row and column, when the running total equals or exceeds a predetermined value, the row or column is determined to be a must-repair or a preferred repair.

Abstract: A network system includes a plurality of networks, a first internetwork apparatus having a plurality of first ports each connected to the plurality of networks, a second internetwork apparatus having a plurality of second ports each connected to the plurality of networks, and a data transmission path connected to the first and second internetwork apparatuses to transmit data mutually between the first and second internetwork apparatuses. In the normal state, each of the plurality of first ports is caused to be able to transmit and receive data to and from one of the plurality of networks and the plurality of second ports are caused not to be able to receive data from the plurality of networks and to be able to transmit data to the plurality of networks.

Abstract: A method and system for trouble shooting and correcting computer software problems. A Trouble Shooting System is launched onto a computer when a user of a software application encounters a problem during use of that software application. The Trouble Shooting System includes a Character Interface, a Trouble Shooting Program, and an Internet-based Trouble Shooting site and server. The Character Interface allows the user to select from a menu of problems, or the user may type into the Character Interface a natural language string to identify the problem. The Trouble Shooting Program generates offset values corresponding to the problem identified by the user. The Trouble Shooting program uses the offset values to locate problem solutions in an Information Store of problem solutions. The problem solutions located in the Information Store are passed to the user for implementation of a correction of the problem.

Abstract: A CPU (central processing unit) including an instruction processor and a data processor is connected with a ROM (read only memory) bus, a RAM (random access memory) bus, and an IO (input-output) bus for inputting/outputting data independently of the ROM and RAM buses. A rewritable register included in a memory access controller stores a set value of the number of wait cycles in an access to a ROM, a set value of the number of wait cycles in an access to a RAM, and a set value for switching an input path in the data processor. These set values can be varied according to a cycle time of a CPU clock signal. In accordance with these set values, insertion of wait cycles in the instruction processor and the data processor is controlled, and it is determined whether or not an input of the data processor is latched.

Abstract: A read/writable memory formed in the same semiconductor chip as a microprocessor is employed in testing a plurality of hardware interrupt service routines initiated by corresponding devices (and components of devices) during a power-on, self-test(POST) of a computer system. The POST is set in the read-only memory(ROM) of the computer system. The read/writable memory, which is ordinarily inoperative during the POST, is used for storing a diagnostic interrupt vector table, which has a list of interrupt numbers and corresponding addresses of the respective interrupt routines. This table is normally subject to change because each device and each of its components have different interrupt service routines, requiring different addresses for the same interrupt number. The random access memory(RAM) has not yet been tested in the POST, and is not regarded as reliable for the hardware interrupt testing and therefore the read/writable memory is used for such testing.

Abstract: A computer system includes a flash memory device for storing BIOS code. The BIOS code is stored in an unprotected area of the flash memory. A boot block, stored in a protected area of the flash memory, is used for rebooting the computer system in the event that the flash memory device becomes corrupted. During normal operation, the BIOS code is updated using a radio link. If the BIOS is corrupted while being updated, a recovery routine stored in the boot block is executed. The recovery routine permits the corrupted BIOS to be reprogrammed using a serial interface instead of the radio link.

Abstract: A method and apparatus for determining if contention exists in a simulated electronic circuit due to multiple simulated drivers contending for the same simulated bus. A contention detection function counts the number of simulated drivers on the simulated bus which are active. If the number of active simulated drivers is greater than one, then an error message is generated reporting contention. The invention is suitable for computer implementation and is particularly well suited for simulation of an integrated circuit. A conversion function can be applied to translate the output of the simulated drivers into a format suitable for processing by the contention detection function and can also retranslate the output of the resolution function into a format suitable for further processing in the simulated electronic circuit. The active state of a simulated driver can be indicated by either a predetermined high voltage level or a predetermined low voltage level.

Abstract: A tamper detect device is provided to a chassis of a system. The tamper detect device provides a signal when the chassis is opened while at least a part of the system is under power. In one embodiment, the signal is used to produce an immediate warning. In another embodiment, the tamper detect device is incorporated into the system and the warning is audio. In another embodiment, the warning is continually provided until the chassis cover is closed, the system is unplugged, or the tamper detect device is bypassed. In another embodiment, the system is a computer system.

Abstract: A high availability shared cache memory in a tightly coupled multiprocessor system provides an error self-recovery mechanism for errors in the associated cache directory or the shared cache itself. After an error in a congruence class of the cache is indicated by an error status register, self-recovery is accomplished by invalidating all the entries in the shared cache directory means of the accessed congruence class by resetting Valid bits to "0" and by setting the Parity bit to a correct value, wherein the request for data to the main memory is not cancelled.Multiple bit failures in the cached data are recovered by setting the Valid bit in the matching column to "0". The processor reissues the request for data, which is loaded into the processor's private cache and the shared cache as well. Further requests to this data by other processors are served by the shared cache.

Abstract: A timer is periodically reset by a software agent executing on a processor. If the timer is not reset within a predetermined period of time, an interrupt is generated. An interrupt handler then periodically resets the timer, and if the timer is not reset within an additional predetermined period of time, the computer system is partially reset.

Abstract: An apparatus for isolating data receiving entity from a data sending entity includes a first data channel, coupled to the data sending entity, and a second data channel, coupled to the data receiving entity. A processor is programmed to compare a plurality of data words received from the first data channel to at least one data word characteristic of a data virus and to assert a control signal when a data word received from the first data channel corresponds to a data word characteristic of a data virus. An optical isolator is capable of isolating the first data channel from the second data channel when the processor detects a data virus. A controllable power supply is responsive to the control signal from the processor and coupled to the optical isolator, which provides power to the optical isolator only when the control signal from the processor is not asserted.

Abstract: A method and apparatus for achieving maximal, full connection in a multi-processor system having a plurality of processors. Each of the multiple processors has a respective memory. The invention includes communicatively connecting the processors. Following a disruption in the communicative connection, the invention collects connectivity information on one of the processors and selects certain of the processors to cease operations, based on the connectivity information collected. The invention further communicates the selection to each of the processors communicatively coupled to the one processor. The selected processors cease operations.

Abstract: According to the present invention, a secured memory comprises a first level security zone having an access code controlling access to the secured memory prior to an issuer fuse being blown, a security code attempts counter preventing access to the secured memory when a predetermined number of attempts at matching the access code have been made prior to resetting the security code attempts counter, a plurality of application zones, each of the plurality of application zones comprising: a storage memory zone, an application security zone having an application zone access code controlling access to the storage memory zone after an issuer fuse has been blown, an application zone security code attempts counter preventing access to the application zone when a predetermined number of attempts at matching the application zone access code have been made prior to resetting the application zone security code attempts counter, an erase key partition having an erase key code controlling erase access to the storage memory

Abstract: An apparatus and method provide for an arithmetic built-in self test (ABIST) of a number of peripheral devices having parallel scan registers coupled to a processor core, all within an integrated circuit. Using the data paths of the processor core, operating logic generates pseudo-random test patterns for the peripheral devices, employing a mixed congruential generation scheme.

Abstract: A network scanner for security checking of application programs (e.g. Java applets or Active X controls) received over the Internet or an Intranet has both static (pre-run time) and dynamic (run time) scanning. Static scanning at the HTTP proxy server identifies suspicious instructions and instruments them e.g. a pre-and-post filter instruction sequence or otherwise. The instrumented applet is then transferred to the client (web browser) together with security monitoring code. During run time at the client, the instrumented instructions are thereby monitored for security policy violations, and execution of an instruction is prevented in the event of such a violation.