Abstract: The present invention is embodied in a system and method for performing spectral analysis of a digital signal having a discrete duration by spectrally decomposing the digital signal at predefined frequencies uniformly distributed over a sampling frequency interval into complex frequency coefficients so that magnitude and phase information at each frequency is immediately available to produce a modulated complex lapped transform (MCLT). The system includes real and imaginary window processors and real and imaginary transform processors. The real and imaginary window processors receive the input signal and apply and compute butterfly coefficients for the real and imaginary parts of the signal to produce resulting real and imaginary vectors, respectively. The real and imaginary transform processors compute spatial transforms on the real and imaginary vectors to produce real and imaginary transform coefficient of the MCLT, respectively.

Abstract: The inventive adder can perform carry look-ahead calculations for a bi-endian adder in a cache memory system. The adder can add one of +/−1, 4, 8, or 16 to a loaded value from memory, and the operation can be a 4 or 8 byte add. The inventive adder comprises a plurality of byte adder cells and carry look-ahead (CLA) logic. The adder cells determine which of themselves is the least significant bit (LSB) byte adder cell. The LSB cell then adds one of the increment values to its loaded value. The other cells add 0x00 or 0xFF, depending upon the sign of the increment value, to a loaded value from memory. Each adder performs two adds, one for a carry-in of 0, and the other for a carry in of 1. Both results are sent to a MUX. The CLA logic determines each of the carries, and provides a selection control signal to each MUX. of the different cells.

Abstract: A method of performing a convolution of an input data stream, the method comprising the steps of: (a) transforming an initial series of input data values into the frequency domain to form initial frequency domain data values; (b) multiplying the frequency domain data values with a set of coefficients so as to form convolved frequency data; (c) transforming the convolved frequency data into a spatial domain so as to form an initial series of output data values; (d) performing steps (a) to (c) on a subsequent series of input data values of the input data stream so as to form a subsequent series of output data values; the subsequent series of input data values overlapping the initial series of input data values; and (e) cross fading overlapping portions of the initial and subsequent output data values.

Abstract: An N-stage finite impulse response (FIR) filter embodying the invention includes a first filter section whose filter coefficients are made either 1 or zero (rather than 1 and −1) in order to produce a first output (i.e., C1) and a second filter section for producing a second output (i.e., C2), which when combined (added to or subtracted from) with the first output produces an output function (i.e., Cn) which is equal to that produced by an N-stage FIR filter implementing filter coefficients having a value of either 1 or −1.

Abstract: The method of the present invention transforms descriptor vectors that characterize items partitioned into groups into a space that discriminates between those groups in a well defined optimal sense. First data is generated that represents a differences between the groups of descriptor vectors. Second data is generated representing variation within the groups of descriptor vectors. A set of component vectors is then identified that maximizes an F distributed criterion function that measures differences of descriptor vectors between groups relative to variations of descriptor vectors within groups. A statistic is generated for subsets of the component vectors. For each particular subset of component vectors, a probability value for the statistic associated with the particular subset is calculated. The subset with the minimum probability value is selected. Finally, one or more of the descriptor vectors for the items are mapped to a space corresponding to the selected subset of component vectors.

Abstract: The invention provides improved techniques for multiplication of signals represented in a normal basis of a finite field. An illustrative embodiment includes a first rotator which receives a first input signal representative of a first normal basis field element (a0 a1 . . . am−1), and a second rotator which receives a second input signal representative of a second normal basis field element (b0 b1 . . . bm−1). A word multiplier receives output signals from the first and second rotators, corresponding to rotated representations of the first and second elements, respectively, and processes the rotated representations w bits at a time to generate an output signal representative of a product of the first and second elements, where w is a word length associated with the word multiplier. The rotated representation of the first element may be given by A[i]=(ai ai+1 . . .

Abstract: The present invention is an incrementor that receives as inputs a 32-dit 1-of-4 operand and a 1-of-2 increment control signal. For each dit of the operand, the present invention determines whether the increment control signal, which is treated as a carry into the least significant dit, propagates into said dit. If so, the value of the dit is incremented. Otherwise, the dit value is output without modification. The present invention also generates a carry out signal if the increment control signal has propagated across all dits.

Abstract: A plurality of units identified by respective addresses are disposed in a register file. Each of the units has a data register for storing data representative of a result of an arithmetic operation, a register for storing an overflow flag indicating the presence or absence of an occurrence of overflow in the arithmetic operation, and a register for storing a sign flag providing an indication of which one of a positive and a negative saturation value should replace the arithmetic operation result in the presence of an occurrence of overflow in the arithmetic operation. Each of the flags is updated in response to a write signal concerning its corresponding register. If at the moment when a data register is fed a read signal, a corresponding overflow flag is set, then either a positive or a negative saturation value, whichever corresponds to the sign flag, is generated on the input side of an arithmetic unit.

Abstract: A system and method for performing multiplication and modular reduction of large integers. The system includes at least one large integer unit, each large integer unit having a multiplier, an adder, and a register. First and second multiplier inputs are applied to the multiplier, and first and second adder inputs are applied to the adder. One output of the multiplier is also applied to the adder. A plurality of large integer units may be connected into a large integer unit array that includes a complementing gate and a latching register. A second output of the multiplier is applied to the first adder input of a next large integer unit, with processing speed increasing as additional large integer units are added to the array.

Abstract: A method and corresponding apparatus for compressing a binary code includes converting an initial flow of data through serial multiplication of values of bits of a signal to be coded, receiving an a coding function, and summing all products of the serial multiplication for a predetermined period of time. The method further provides that discrete values of the coding function are used as the coding function, the coding function is a piecewise continuous function in a form of a Gaussian pulse with a frequency fill, computations of a Duamel sequence are used during conversion of the code, and the initial data and discrete values of the coding function are used as arguments of the sequence.

Abstract: A multi-function look-up table for determining output values for predetermined ranges of a first mathematical function and a second mathematical function. In one embodiment, the multi-function look-up table is a bipartite look-up table including a first plurality of storage locations and a second plurality of storage locations. The first plurality of storage locations store base values for the first and second mathematical functions. Each base value is an output value (for either the first or second function) corresponding to an input region which includes the look-up table input value. The second plurality of storage locations, on the other hand, store difference values for both the first and second mathematical functions. These difference values are used for linear interpolation in conjunction with a corresponding base value in order to generate a look-up table output value.

Abstract: A radially distributed transverse filter includes a plurality of delay lines of substantially equal electric length sequentially coupled at a like plurality of nodes. The nodes are distributed equidistant from a common position, for example positioned at vertices of a polygon. A plurality of attenuators are distributed radially about the common position and coupled between the nodes and the common position. An adder is located substantially at the common position for summing the attenuator outputs. In this manner, the respective propagation delays of each tap are substantially similar, and imprecision due to variation in propagation delay is therefore mitigated and/or substantially eliminated. The invention has application to high-frequency digital and analog transverse filters, for example filters for equalizers used in Partial Response Maximum Likelihood (PRML) circuits employed in contemporary magnetic recording systems.

Abstract: A floating point arithmetic logic unit includes two rounding units that select between an incremented, unincremented, and complemented result from a carry propagate adder. A fast rounding unit selects a result as an approximation based on the equality or inequality of the exponents of the operands, the relative sizes of the mantissas and the presence of a guard bit. The result selected by the fast rounding unit is received by a leading zero count unit, which counts the leading zeros of the result. A second slower rounding unit meanwhile makes a selection between the incremented, unincremented, and complemented results based on the rounding mode, the sign of the result and whether the result is exact. The result is inexact when both the most significant bit and the guard bit are equal to one. While the slower rounding unit may take longer to determine the appropriate selection, the result selected is the most accurate.

Abstract: A floating point unit includes a rounding unit that rounds the two least significant bits of a sum. After a sum of the two mantissas is generated the at least one least significant bit is separated from the sum. When addition is performed, two least significant bits are separated from the sum. A half add unit may be used to generate the sum along with a set of carry data, and thus at least one least significant bit of the carry data is also separated. A rounding unit receives the separated at least one least significant bit of the sum and carry data and produces a carry in bit as well as rounded at least one least significant bit. The sum and carry data are then summed in a later stage of the floating point unit to form both a unincremented sum and an incremented sum, which are stored in a multiplexer. The carry in bit is used to select one of the unincremented sum and incremented sum.

Abstract: A set of scaled weighing coefficients is employed in the intrinsic multiplication stage of a six-stage DCT/IDCT fast algorithm for one of two one-dimensional DCT/IDCT operations so that a corresponding stage of the DCT/IDCT fast algorithm for the other one of the one-dimensional DCT/IDCT operations can be omitted. Accordingly, the number of multiplication operations for two-dimensional DCT/IDCT processing is reduced in order to achieve a higher processing speed.

Abstract: One multiplier 13 operated at a normalized frequency 4 is provided to multiply the elements of DCT transformation coefficients and the elements of input data, and the multiplication results are added by a cumulative adder 15 to determine cumulative addition results corresponding to the sum (x0+x7) and the difference (x0−x7) of a pair of elements (x0, x7) of data to be outputted from a one-dimensional DCT operation circuit 1. The paired cumulative addition results are added and subtracted by an adder 17 and a subtracter 18, respectively, to determine the elements (x0, x7). The operations are performed specific times the number of which is one half of the number of elements of a column of the matrix of the input data to determine the elements of a column of the matrix of the output data and are performed specific times the number of which is equal to the number of elements of a row of the matrix or the input data to determine all the elements of the matrix of the output data.

Abstract: A scheme for carrying out modular calculations which is capable of carrying out modular calculations using redundant binary calculation even when a number of bits of the mantissa (dividend) is larger than a number of bits of the modulus (divisor). In this scheme, the divisor c in the divisor register is left shifted by (i−j) digits when a number of digits j of the divisor c is less than a number of digits i that can be stored in the divisor register, and the modular reduction a mod c is calculated up to (i−j)-th decimal place using the dividend a and the left shifted divisor c.

Abstract: The present invention is an apparatus to normalize a floating point number. The apparatus has a first storage area comprising the floating point number. The floating point number comprises an exponent field and an explicit bit. The apparatus further comprises a circuit to normalize the floating point number when the explicit bit is not set and the exponent field has a first predetermined value identifying a redundant denormal encoding of the floating point number. Otherwise the encoding of the number is not changed by the circuit.

Abstract: A method and a circuit for multiplication on a finite field which operate fast and involve a small circuit scale. There is provided a multiplication circuit on a finite field for multiplication of two arbitrary elements a=(a.sub.0, a.sub.1, . . . , a.sub.m-1) and b=(b.sub.0, b.sub.1, . . . , b.sub.m-1) of a Galois field GF(2.sup.m) utilizing a polynomial .function.=x.sup.m +x.sup.m-1 + . . . +x+1 as a polynomial to derive the GF(2.sup.

Abstract: A parallel adder is disclosed. The parallel adder includes a number of computational cells that operate to generate odd sum bits based on generate and propagate terms recursively computed and a plurality of carry-in bits. The parallel adder further includes a number of selection cells that are independent of the computational cells and operate to select and output even sum bits from a number of candidate sum bits, the selection being made in accordance with predetermined ones of said recursively computed generate and propagate terms.